PAR

After a design has undergone the necessary translation to bring it into the NCD (Circuit Description) format, it is ready for placement and routing. This phase is done by PAR (Xilinx's Place and Route program). PAR takes an NCD file, places and routes the design, and outputs an NCD file which is used by the bitstream generator (BitGen). The output NCD file can also act as a guide file when you reiterate placement and routing for a design to which minor changes have been made after the previous iteration.

In the Xilinx Development System, PAR places and routes a design using a combination of two methods.

• Cost-based - This means that placement and routing are performed using various cost tables which assign weighted values to relevant factors such as constraints, length of connection, and available routing resources. Cost-based placement and cost-based routing are further described in the “PAR Operation” section.
  
  
• Timing-Driven - The Xilinx timing analysis software enables PAR to place and route a design based upon your timing constraints. Timing-driven PAR is described in the “PAR and the Timing Analysis Software” section.
  
  

Flow through the PAR module is shown in the following figure. The figure shows a PAR run that produces a single output design file.

Figure 10.1 PAR Flow