Hierarchy Changes in Annotated Designs

NGDAnno may flatten part of your original design hierarchy when generating a simulation netlist under the following conditions.

• Logical correlation loss on a CLB due to logic optimization and logic replication during mapping
  
  
• Logic mapped in this way is located in different parts of the design hierarchy
  
  

For example, if a flip-flop with the hierarchical name A/B/X is merged with a flip-flop named A/C/Y, and the resulting CLB is affected by optimization or logic replication, hierarchical blocks A/B and A/C are flattened out of the netlist. The two flip-flops now lie at the same level of hierarchy (the A level) and are replaced by the CLB physical model.

The netlist readers NGD2EDIF, NGD2VER, and NGD2VHDL generate a warning for each hierarchical block that is flattened.