NGD2VER Files

This section describes the NGD2VER input and output files.

Input Files

Input to NGD2VER can be either of the following files.

• NGA - a back-annotated logical design file produced by NGDAnno, containing Xilinx primitives.
  
  
• NGD - a logical design file produced by NGDBuild, containing Xilinx simulation primitives.
  
  

Output Files

Output from NGD2VER consists of the following files.

• V file - a Verilog HDL file containing the netlist information obtained from the input NGD or NGA file. This file is a simulation model and cannot be synthesized or used in any other manner than simulation. This netlist uses simulation primitives which may not represent the true implementation of the device; however, the netlist represents a functional model of the implemented design. Do not modify this file.
  
  
• SDF file - an SDF (Standard Delay Format) file containing delays obtained from the input file. NGD2VER only generates an SDF file if the input is an NGA file, which contains timing information. The SDF file generated by NGD2VER is based on SDF version 2.1.
  
  

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  NOTE

  The SDF file should only be used with the Verilog file. Do not use the SDF file with the original design or with the product of another netlist writer.

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• LOG file - an optional log file created if you enter the -log option on the NGD2VER command line. It contains all the messages generated during the execution of NGD2VER.
  
  
• TV file - an optional test fixture file created if you enter the -tf option on the NGD2VER command line.
  
  
• PIN file - an optional Cadence signal-to-pin mapping file. NGD2VER generates a PIN file if the input file contains routed external pins and you have specified a -pf command line option.
  
  

The files have the same root name as the NGD or NGA file unless you specify otherwise.