XC4000E/L/EX/XL/XV/XLA, Spartan, SpartanXL, Virtex, and XC5200 devices also have a global control signal (GTS) that tristates all output pins. This allows you to isolate the actual device part during board level testing. You can also tristate the FPGA device outputs during board level simulation to assist in debugging simulation. In most cases, GTS is deactivated so that the outputs are active.
Although the STARTUP component also gives you the option of controlling the global tristate net from an external pin, usually it is used for controlling global reset. In this case, the GTS pin can be left unconnected in the design entry phase, and it will float to its inactive state level. The global tristate net, GTS, is in implemented designs even if a STARTUP block is not instantiated.
You can deactivate GTS by driving it Low in your test fixture file, or by connecting the GTS pin to GND in your input design.
The general procedure for specifying GTS is similar to that used for specifying the global set/reset signals, GSR and GR. You define the global tristate signal with the Verilog macro, GTS_SIGNAL. You must declare the global tristate signal either as a Verilog wire or reg. If you do not want to specify GTS for simulation, you do not need to change anything in your design or test fixture.
The net name you select, and whether you specify the net as a Verilog reg or a wire, depends on if you have a STARTUP block instantiated in your design, and if you have a signal connected to the STARTUP GTS pin.
If a STARTUP block is not in your design, name the global tristate wire test_fixture_module.design_instance.GTS, and declare the signal as a Verilog wire data type in your design netlist.
If there is a STARTUP block in your design and the GTS pin is connected to a net, the value of GTS_SIGNAL should be set to the name of the net connected to the GTS pin on the STARTUP symbol. The signal you toggle at the beginning of simulation is the port or signal in your design that is used to control global tristate. This is usually an external input port in the Verilog netlist, but can be a wire if global tristate is controlled by internal logic in your design.
Xilinx recommends that you name the main module in your test fixture file test to be consistent with the name of the test fixture module that is written further in the design flow by NGD2VER. If this naming consistency is maintained, you can use the same test fixture file for simulation at all stages in the design flow with minimal modification.
The GTS signal in XC4000E/L/EX/XL/XV/XLA, Spartan, SpartanXL, Virtex, and XC5200 devices is active-High. This macro is not used in timing simulation when there is a STARTUP block in your design and the GTS pin is connected.
For post-NGDBuild and post-route timing simulation, the test fixture template (TV file) produced by NGD2VER with the -tf option contains most of the code described previously for defining and driving GTS.
However, in cases where you have a signal controlling the STARTUP block, you must manually edit the test fixture template file generated by NGD2VER to specify the control signal for GTS.
When you do not have a STARTUP block in your design, you can use the same test fixture file with little or no modification if you use the guidelines in the following example.
The following is an example of how you can drive the GTS signal in a test fixture file at the beginning of a pre-NGDBuild RTL or post-synthesis functional simulation. The global tristate net is named GTS in XC4000E/L/EX/XL/XV/XLA, Spartan, SpartanXL, Virtex or XC5200 designs when there is not a STARTUP block. The Verilog macro defining the global net must be named GTS_SIGNAL because this is the name of the predefined macro used to model the global tristate signal in the Xilinx Verilog UNISIM simulation models. Use the following guidelines.
module my_design;
wire GTS;module test;
`define GTS_SIGNAL test.uut.GTS;
initial
begin
`GTS_SIGNAL = 0;Asserting global tristate when the STARTUP block is specified in your design is similar to asserting global tristate without a STARTUP block. There are two primary differences, as follows.
`define GTS_SIGNAL net_connected_to_GTS_pininitial
begin
GTS_user_control_signal = 1;
#100 GTS_user_control_signal = 0;In the following figure, the design contains a STARTUP block, and the GTS pin on STARTUP is connected to an external input named mygts.
Figure 17.6 Verilog User-Controlled Inverted GTS |  |
The STARTUP_VIRTEX block differs slightly in that is has no outputs.
The external input, mygts, is declared as a Verilog register. A `define directive setting GTS_SIGNAL to the name of the net connected to the GTS pin is required to connect the user logic to the global GTS model in the UNISIM simulation models for output buffers (OBUF, OBUFT, and so on). The following is an example of a test fixture.
module test;
reg mygts;
`define GTS_SIGNAL test.uut.gts_in;
.
.
.
initial
begin
mygts = 1; ; ;// if you wish to tristate the
// device;
#100 mygts = 0; ; ; ; ;// deactivate GTSFor post-route timing simulation, the procedure is similar, except you must omit the define statement for GTS_SIGNAL because it conflicts with the GTS net driver.
module test;
reg mygts;
// `define GTS_SIGNAL test.uut.gtsin
initial
begin
mygts = 1; ; ;// if you wish to tristate the
// device;
#100 mygts = 0; // deactivate GTSFor Unified Library functional simulation, define a wire named GTS, and set the GTS_SIGNAL macro to test.GTS. Toggle GTS_SIGNAL as shown in the following example.
module test;
wire GTS;
`define GTS_SIGNAL test.GTS
initial
begin
force `GTS_SIGNAL = 1; ; ; ; ;// if you wish to
// tristate the
// device;
#100 force `GTS_SIGNAL = 0; // deactivate GTSFor post-NGDBuild functional simulation, the actual net exists and must be further qualified by the design instance scope, uut, as shown here.
module test;
// wire GTS;
// `define GTS_SIGNAL test.GTS
`define GTS_SIGNAL test.uut.GTS
initial
begin
force `GTS_SIGNAL = 1; ; ; ; ;// if you wish to
// tristate the
// device;
#100 force `GTS_SIGNAL = 0; ;// deactivate GTSFor post-route timing simulation, you can use the same test fixture.
