The Logical DRC Tests

The Logical DRC performs six types of checks.

• Block check
  
  
• Net check
  
  
• Pad check
  
  
• Clock buffer check
  
  
• Name check
  
  
• Primitive pin check
  
  

The following sections describe these tests.

The Block Check

The block check verifies that each terminal symbol in the NGD hierarchy (that is, each symbol that is not resolved to any lower-level components) is an NGD primitive. A block check failure is treated as an error. As part of the block check, the DRC also checks user-defined properties on symbols and the values on the properties to make sure they are legal.

The Net Check

The net check determines the number of NGD primitive output pins (drivers), tristate pins (drivers) and input pins (loads) on each signal in the design. If a signal does not have at least one driver (or one tristate driver) and at least one load, a warning is generated. An error is generated if a signal has multiple non-tristate drivers or any combination of tristate and non-tristate drivers. As part of the net check, the DRC also checks user-defined properties on signals and the values on the properties to make sure they are legal.

The Pad Check

The pad check verifies that each signal connected to pad primitives obeys the following rules.

• If the PAD is an input pad, the signal to which it is connected can only be connected to these types of primitives.
  
  
  • A BUF primitive
    
    
  • A CKBUF primitive
    
    
  • A PULLUP primitive
    
    
  • A PULLDOWN primitive
    
    
  • BSCAN primitive
    
    The input signal can be attached to multiple primitives, but only one of each of the above types. For example, the signal can be connected to a BUF primitive, a CKBUF primitive, and a PULLUP primitive, but it cannot be connected to a BUF primitive and two CKBUF primitives. Also, the signal cannot be connected to both a PULLUP primitive and a PULLDOWN primitive. Any violation of the rules above results in an error, with the exception of signals attached to multiple pullups or pulldowns, which produces a warning. A signal which is not attached to any of the above types of primitives also produces a warning.
    
    
• If the PAD is an output pad, the signal it is attached to can only be connected to these primitive outputs.
  
  
  • A single BUF primitive output, or
    
    
  • A single TRI primitive output, or
    
    
  • A single BSCAN primitive
    
    

In addition to

• A single PULLUP primitive, or
  
  
• A single PULLDOWN primitive
  
  Any other primitive output connections on the signal results in an error.
  
  If the condition above is met, the output PAD signal may also be connected to one CKBUF primitive input, one BUF primitive input, or both.
  
  
• If the PAD is a bidirectional or unbonded pad, the signal it is attached to must obey the rules stated above for input and output pads. Any other primitive connections on the signal results in an error. The signal connected to the pad must be configured as both an input and an output signal; if it is not, you receive a warning.
  
  
• If the signal attached to the pad has a connection to a top-level symbol of the design, that top-level symbol pin must have the same type as the pad pin, except that output pads can be associated with tristate top-level pins. A violation of this rule is a warning.
  
  
• No signal can be connected to multiple pads (an error) or to multiple top-level pins (a warning).
  
  

The Clock Buffer Check

The clock buffer configuration check verifies that the output of each clock buffer primitive is connected to only inverter, flip-flop or latch primitive clock inputs, or other clock buffer inputs. Violations are treated as warnings.

The Name Check

The name check verifies the uniqueness of names on NGD objects as defined below. The tests, and the messages reported by a violation of the tests, are

• Pin names must be unique within a symbol. A violation is an error.
  
  
• Instance names must be unique within the instance's position in the hierarchy (that is, a symbol cannot have two symbols with the same name under it). A violation is a warning.
  
  
• Signal names must be unique within the signal's hierarchical level (that is, if you push down into a symbol, you cannot have two signals with the same name). A violation is a warning.
  
  
• Global signal names must be unique within the design. A violation is a warning.
  
  

The Primitive Pin Check

The primitive pin check verifies that certain pins on certain primitives are connected to signals in the design. The check tests these pins on these NGD primitive types.

If one of these pins is not connected to a signal, you receive a warning.