Schematic tools provide a graphic interface for design entry. You can use these tools to connect symbols representing the logic components in your design. You can build your design with individual gates, or you can combine gates to create functional blocks. This section focuses on ways to enter functional blocks using library elements and LogiBLOX, the logic-design/synthesis tool.
The following section discusses primitives and macros, which are the “building blocks” of component libraries.
Xilinx FPGA libraries provide primitives as well as common high-level macro functions. Primitives are basic circuit elements, such as AND and OR gates. Each primitive has a unique library name, symbol, and description. Macros contain multiple library elements, which can include primitives and other macros.
There are two types of macros you can use with Xilinx FPGAs. Soft macros, available for all FPGAs, have pre-defined functionality, but have flexible mapping, placement, and routing. Relationally placed macros (RPMs) have fixed mapping and relative placement. However, they are only available for XC4000E/X, XC5200, Spartan series, and Virtex devices.
Macros are not available for Synthesis. This is because synthesis tools have their own module generators and do not require RPMs. If you wish to override the module generation, you can instantiate LogiBLOX modules. For most leading-edge synthesis tools, this does not offer an advantage unless it is for a module that cannot be inferred.
Schematics usually contain hierarchy, which is important for the following reasons.
A specific hierarchical name identifies each library element, unique block, and instance you create. For example, the last three terms in the name
/Acc/alu_1/mult_4/8count_3/4bit_0/mux_1/or2
might refer to the 2-input OR gate in the first instance of a multiplexer in a 4-bit counter.
Xilinx strongly recommends that you name the components and nets in your design. In schematic editors, component names and net names are preserved and used by EPIC (Editor for Programmable Integrated Circuits). The component names and net names are also used for back-annotation and appear in the debug and analysis tools. If you do not name your components and nets, the schematic editor automatically generates the names. For example, if left unnamed, the software might name the previous example as follows.
/$1a123/$1b942/$1c23/$1d235/$1e121/$1g123/$1h57
It can be very difficult to analyze circuits with automatically generated names, since they only have meaning for Xilinx software.
LogiBLOX is a tool which can generate a variety of variable-sized MSI- and LSI-level design building blocks such as adders, counters, decoders, and shift registers. These modules complement the Xilinx macro libraries, which contain simpler, fixed-size logic and gate functions. LogiBLOX also integrates these modules into your design. For further information, see the LogiBLOX Reference/User Guide.
LogiBLOX does not currently support the Virtex family of FPGAs.
