Before you implement your design, you may want to constrain it within certain timing or placement parameters. You can specify mapping, block placement, and timing specifications during design entry. The following sections describe these methods.
You can specify how a particular block of logic is mapped into CLBs using a CLBMAP for XC3000 FPGAs; an FMAP or HMAP for XC4000E/X and Spartan series FPGAs; or an FMAP or F5MAP for XC5000 FPGAs. These mapping symbols can be used in your schematic. However, if you overuse these specifications, it may be harder to route your design.
Block placement can be constrained to a specific location, to one of multiple locations, or to a location range. Locations can be specified in the schematic, with synthesis tools, or in the User Constraint File (UCF). Poor block placement can adversely affect both the placement and the routing of a design. Typically, block placement defines I/O placement.
You can specify timing requirements for paths in your design directly in your schematic. PAR (the Xilinx Place and Route program) uses these timing specifications to achieve optimum performance when placing and routing your design. See the Timing Analyzer Reference/User Guide and the Constraints Editor User Guide for a detailed explanation of timing specifications.
