TRACE (Timing Reporter and Circuit Evaluator)

TRACE is a static timing analysis utility that can be used to see if the constraints imposed upon your design have been met. When applied, TRACE issues a report enumerating timing constraint violations, such as path delay errors, net delay errors, net skew errors, and other relevant information. Three user-selectable reporting levels are available. They are summary, error, and verbose, with summary reporting being a brief report and verbose reporting being the most detailed. The timing report (or TWR) file lists each constraint on one line. The information in the report can be used to evaluate the timing of a design and make adjustments if necessary.

TRACE can also be used to do timing analysis on a design even if there are no user defined timing constraints.

Input files to Xilinx TRACE are the following.

• A mapped NCD design. If you are performing timing verification, the design should also be placed and routed.
  
  
• PCF, an optional user-modifiable ASCII Physical Constraints File produced by the MAP program. Timing constraints can be written into this file.
  
  

For more information on TRACE, see the “TRACE” chapter in the Development System Reference Guide.

To run TRACE from the Design Manager, use the Timing Analyzer. Refer to the Timing Analyzer Reference/User Guide for details.

Figure 3.6 TRACE