FPGA Design Techniques

The Xilinx FPGA architecture is best suited for synchronous design. Strict synchronous design ensures that all registers are driven from the same time base with no clock skew. The following sections outline several tips for producing high-performance synchronous designs.

Design Size and Performance

Information about design size and performance can help you to optimize your design. When you place and route your complete design, the resulting report files list the number of CLBs, IOBs and other device resources available. A first pass estimate can be obtained by processing the design through the map program.

If you want to determine the design size and performance without running automatic implementation software, you can quickly obtain an estimate from a rough calculation based on the Xilinx FPGA architecture. See The Programmable Logic Data Book for more information on all Xilinx FPGA architectures.

Global Clock Distribution

Xilinx clock networks guarantee extremely small clock skew values. The following table lists the resources available for several Xilinx FPGA families.

Table 3_1 Global Clock Resources

FPGA Family	Resource	Number	Destination Pins
XC3000A/L XC3100 XC3100A/L	GCLK	1	Clock
XC4000E/L	BUFGP BUFGS	4 4	K, IK K, IK
XC4000EX/XL	BUFG BUFGLS BUFGE BUFFCLK	1 8 8 4	K, IK K, IK K, IK K, IK
XC5200	BUFG	4	Clock or Control
Spartans	BUFGP BUFGS	4	Clock
Virtex	BUFG	4	Clock

NOTE

For global clock information about the new XC4000XV and XC4000XLA device families, refer to the Xilinx website at (http://www.xilinx.com/products/products.htm).

XC4000 BUFGP and BUFGS also connect to control pin and logic inputs; however, limited routing resources can add extra delay on these loads.

Other Synchronous Design Considerations

Other considerations for achieving a synchronous design include the following.

Use clock enables instead of gated clocks to control the latching of data into registers. See the “Gated Clock” figure and the “Synchronous Design Using Data Feedback” figure.
If your design has more clocks than the number of global clock distribution networks, try to redesign to reduce the number of clocks. Otherwise, put the clocks that have the lowest fan-out onto normally routed nets, and specify a low MAXSKEW rating. Remember that a clock net routed through a normal net has skew.

Data Feedback and Clock Enable

The timing diagram indicates that this implementation can lead to clock glitches; this can cause the flip-flop to clock at the wrong time.

Figure 3.9 Gated Clock

The “Synchronous Design Using Data Feedback” figure shows a synchronous alternative to the gated clock using a data path. The flip-flop is clocked at every clock cycle and the data path is controlled by an enable. When the enable is Low, the multiplexer feeds the output of the register back on itself. When the enable is High, new data is fed to the flip-flop and the register changes its state. This circuit guarantees a minimum clock pulse width and it does not add skew to the clock. The XC4000, XC5200, and Virtex flip-flops have a built-in clock-enable (CE).

Figure 3.10 Synchronous Design Using Data Feedback

Counters

Cascading several small counters to create a larger counter is similar to a gated clock. For example, if two 8-bit counters are connected, the TC (terminal counter) of the first counter is a large AND function gating the second clock input. Using the CE input, you can create a synchronous design as shown in the following figure. In this case, the TC (terminal counter) of the first stage is connected directly to the CE of the second stage.