Entering EPIC

1. With the Calc project loaded into the Xilinx Design Manager project view, select the version and revision for which you wish to examine the routed design (e.g. ver1 rev1). Select Tools EPIC Design Editor from the menu bar. Alternatively, you can click on the EPIC icon within the Toolbox on the right-hand side of the Xilinx Design Manager window to bring up EPIC.
   
   

   Figure 8.1 EPIC Icon

   The editor appears, as shown in the following figure, with the Calc design automatically loaded.
   
   
2. The editor is a graphic representation of the FPGA or CPLD. Zoom in to the device by selecting View Zoom In or clicking on the middle mouse button; zoom out by selecting View Zoom Out or clicking the right mouse button.
   
   
3. Pan around the device by holding down the middle mouse button and dragging. You may also pan around the device by dragging the box in the context window (in the upper right-hand corner of the EPIC window) with the middle mouse button.
   
   
4. Two types of blocks are shown in the editor. The IOBs appear around the periphery of the device, and the CLBs appear in the middle. Pan around the die to see how the design was placed and routed in the device. Used blocks are highlighted, and the signal nets connecting them are shown as highlighted traces.
   
   
5. Looking at the routed design, observe how the global clock was carried through from the schematic level to the routed design.
   
   

Figure 8.2 Main EPIC Screen, XC4003E-4-PC84