Implementation Styles

Some LogiBLOX modules can be implemented in more than one way within the Xilinx architectures. The implementation methods are called “styles.” Some styles use fewer Configurable Logic Blocks (CLBs) at the expense of speed, while other styles use more CLBs to achieve faster performance.

Types of Modules

This section covers modules that require the specification of an implementation style. A STYLE attribute value can be assigned to the LogiBLOX modules listed in the following table.

Table 3_2 Style Specification for Modules

Module	Possible Style
Accumulators Adders/Subtracters Counters¹ 1. The STYLE attribute applies to binary counters only; it is ignored for counters with a non-binary encoding.	ALIGNED ALIGNED RPM FAST 3KA MAXIMUM SPEED MINIMUM AREA RIPPLE CARRY UNALIGNED UNALIGNED RPM
Comparators	ALIGNED ALIGNED RPM EDGE DECODE MAXIMUM SPEED MINIMUM AREA RIPPLE CARRY TREE UNALIGNED UNALIGNED RPM WIRED AND
Data Registers	D-TYPE LATCHES
Decoders² 2. The STYLE attribute values listed here apply to the xc5200 family only.	CASCADE MAXIMUM SPEED NORMAL GATES
Multiplexers	CASCADE F5_MUX MAXIMUM SPEED MINIMUM AREA NORMAL GATES WIRED AND
Simple Gates³ 3. The style attribute applies to Type_1 Gates only.	CASCADE EDGE DECODE MAXIMUM SPEED MINIMUM AREA NORMAL GATES WIRED AND

To have LogiBLOX automatically select the best style based on a speed or area preference, specify the MAXIMUM SPEED or MINIMUM AREA values. These attribute values indicate that LogiBLOX should choose the implementation style that best meets your needs in the target architecture.

NOTE

A particular module's choice of styles will vary depending on the device family selected or the type of logic used.

The following list summarizes the optimal style definitions by module and device family.

Accumulators, Adders/Subtracters, Counters

XC3000

MAXIMUM SPEED:FAST 3KA
MINIMUM AREA:RIPPLE CARRY

XC4000, XC5200

MAXIMUM SPEED:ALIGNED RPM
MINIMUM AREA:ALIGNED RPM

Comparators

XC3000

MAXIMUM SPEED:TREE
MINIMUM AREA:RIPPLE CARRY

XC4000 (Equality Comparisons)

MAXIMUM SPEED:ALIGNED RPM
MINIMUM AREA:TREE

XC4000 (Equality and Magnitude Comparisons)

MAXIMUM SPEED:ALIGNED RPM
MINIMUM AREA:ALIGNED RPM

XC5200

MAXIMUM SPEED:ALIGNED RPM
MINIMUM AREA:ALIGNED RPM

Multiplexers

XC3000, XC4000 (< 4-input Muxes)

MAXIMUM SPEED:NORMAL GATES
MINIMUM AREA:NORMAL GATES

XC3000, XC4000 (> 4-input Muxes)

MAXIMUM SPEED:WIRED AND
MINIMUM AREA:WIRED AND

XC5200 (< 16-input Muxes)

MAXIMUM SPEED:CASCADE
MINIMUM AREA:F5_MUX

XC5200 (> 16-input Muxes)

MAXIMUM SPEED:CASCADE
MINIMUM AREA:CASCADE

Simple Gates

XC3000, XC4000 (<= 4-input AND gates or > 4-input non-AND gates)

MAXIMUM SPEED:NORMAL GATES
MINIMUM AREA:NORMAL GATES

XC3000, XC4000 (> 4-input AND gates)

MAXIMUM SPEED: WIRED AND
MINIMUM AREA:WIRED AND

XC5200 (<= 7-input gates)

MAXIMUM SPEED:NORMAL GATES
MINIMUM AREA:NORMAL GATES

XC5200 (> 7-input gates)

MAXIMUM SPEED:CASCADE
MINIMUM AREA:CASCADE

Types of Styles

This section is an alphabetical reference of available styles.

ALIGNED, ALIGNED RPM, UNALIGNED, and UNALIGNED RPM

These styles apply to Accumulators, Adders/Subtracters, Comparators, and Counters. Aligned and Unaligned apply to all Spartan and XC4000 devices. Aligned RPM and Unaligned RPM apply to all Spartan, XC4000, and XC5200 devices.

Both styles use the fast carry logic and, therefore, constitute the fastest and smallest implementation styles for Spartan, XC4000, and XC5200 devices. On Spartan and XC4000 devices, the logic is aligned into a vertical column of CLBs when the Aligned option is selected. On XC5200 devices, the logic is aligned into two vertical columns of CLBs.

In RPM modules, the CLBs comprising the module maintain a constant relative position to each other.

In aligned modules, the initialization bit, i, occupies a CLB by itself and the first bit of the module, bit 0, starts a new CLB. As a result, the even bits of the module are aligned with CLB boundaries. In Spartan and XC4000 devices, the bits are grouped in twos and in XC5200 devices, bits are grouped in fours. Each group of bits occupies a single CLB.

Bits (0, 1), (2, 3), (4, 5), … share the same CLBs in Spartan and XC4000 families
Bits (0, 1, 2, 3), (4, 5, 6, 7), … share the same CLBs in XC5200 families

In unaligned modules, the initialization bit, i, shares the same CLB as bit 0. The rest of the bits are grouped and occupy CLBs as follows.

Bits (i, 0), (1, 2), (3, 4), (5, 6), … share the same CLBs in XC4000 families
Bits (i, 0, 1, 2), (3, 4, 5, 6), … share the same CLBs in XC5200 families

CASCADE

This style applies to Decoders, Simple Gates, and Multiplexers in XC5200 devices.

When used in Decoders, this style implements functions using the dedicated carry logic multiplexer and function generators to serialize the decoding logic chain.
When used in Simple Gates, this style implements functions using carry multiplexers to combine 4-input sub-functions. Wide functions implemented with this style are significantly faster and smaller.
When applied to Multiplexers, this style uses carry multiplexer logic that is unique to this family. It is expandable with little area and timing impact.

Note that specifying the cascade style has placement implications. Specifically, the logic becomes aligned into a vertical column of CLBs.

D-TYPE

This style applies to Data Registers. When this style is used, regular flip-flops are constructed.

EDGE DECODE

This style applies to Simple Gates and Comparator symbols in XC4000 devices.

When applied to Type 1 Simple Gate symbols, this style uses wide edge-decoders to implement the AND and NAND functions.
When applied to equality operations of Comparators, this style uses a wired-AND implementation built using wide edge-decoders to detect patterns being applied through I/Os. You may only use it to compare a value against a constant.

Wide I/O decode functions using this style can be significantly faster than CLB-based implementations. The I/Os that are used in a decode or compare function will be placed on one edge of the chip.

FAST 3KA

This style applies to Accumulators, Adders/Subtracters, and Counters in XC3000A and XC3100A devices. It uses a gate implementation carry look-ahead adder. It is the fastest implementation style for carry-based modules in XC3000A and XC3100A devices. Modules implemented with this style are 50 percent larger but 30 percent faster than those implemented with the RIPPLE CARRY style.

F5_MUX

This style applies to Multiplexers in XC5200 devices and uses the fast carry logic technique that is unique to this family. It is most efficient for multiplexers with 16 inputs or less.

LATCHES

This style applies to Data Registers in XC4000EX, XC4000XL, XC4000V, and XC5200 devices. When used, the normal CLB registers are configured as transparent level-sensitive latches.

MAXIMUM SPEED

This style applies to Accumulators, Adders/Subtracters, Counters, Comparators, Decoders (XC3000 and XC5200 devices only), Multiplexers, and Simple Gates. It ensures that the fastest implementation style for the target architecture is used.

MINIMUM AREA

This style applies to Accumulators, Adders/Subtracters, Counters,
Comparators, Multiplexers, and Simple Gates. It ensures that the smallest implementation style for the target architecture is used.

NORMAL GATES

This style applies to Decoders (XC3000 and XC5200 devices only), Multiplexers, and Simple Gates. It uses a gate implementation, that is, CLB look-up tables.

RIPPLE CARRY

This style applies to Accumulators, Adders/Subtracters, Counters, and Comparators in the XC3000A, XC4000, and XC5200 families. This style is not as efficient as the ALIGNED RPM style for XC4000 and XC5200 devices.

When applied to Accumulators, Adders/Subtracters, and Counters, the RIPPLE CARRY style uses a gate implementation style.

The RIPPLE CARRY style is smaller but slower for XC3000A devices than the FAST 3KA style.
When applied to Comparators, this style uses a gate implementation ripple propagation compare and applies only to equality comparisons. The results are rippled from the MSB to the LSB. The RIPPLE CARRY style is the style that uses the fewest CLBs for equality comparisons in XC3000A devices.

TREE

This style applies to Comparators in XC3000A, XC4000, and XC5200 devices. It uses a gate implementation tree magnitude comparison and applies to all comparison operations in supported devices. It is the only way of implementing magnitude comparisons in XC3000A devices. For XC4000 and XC5200 devices, this style is not as efficient as the ALIGNED RPM or UNALIGNED RPM style.

WIRED AND

This style applies to Simple Gates, Multiplexers, and Comparators in XC3000A and XC4000 devices. Wide input functions with this style can be significantly faster.

This style uses tristate buffers (TBUFs) and horizontal long-lines. Logic is aligned into horizontal rows of CLBs next to the horizontal long lines.

Modules implemented in this style can only be as wide as the number of tristate buffers per horizontal long-line in the target device.

When applied to Simple Gates, this style implements AND and NAND functions using a wired-AND implementation
When applied to Multiplexers, this style uses wired-MUX implementation and increases the speed of wide MUX functions significantly, particularly in XC3000A and XC4000 devices.
When applied to Comparators, this style uses a wired-AND implementation and applies to equality comparisons in XC3000A and XC4000 devices. It uses the same number of CLBs as the RIPPLE CARRY style.

NOTE

The number of TBUFs allowed in a row for a particular device is limited. PAR may fail if the Bus Width selected for the module is greater than the number of TBUFs allowed in a row for the specific device. Refer to the The Programmable Logic Data Book for the number of TBUFs allowed in the target device.