CLOCK DIVIDER

The Clock Divider module uses a Linear-Feedback-Shift-Register (LFSR) counter and decoder to generate an output pulse train that is a function of the clock input and the control attributes.

The Clock Output period is a multiple of the Clock period specified by the Clock Divisor attribute. Even multiples of the Clock period produce a 50 percent duty cycle on the Clock Output, while odd multiples produce a Low Output for one extra Clock period. You can use the Output Duty Cycle attribute to control the duty cycle if you need values other than 50 percent.

The Bus Width field is not applicable to this module and is therefore disabled.

Figure 4.4 The Clock Divider Module

Figure 4.5 Simple Clock Divider Example

Input Pins

The Asynchronous Control input is a level-sensitive input. When this input is High, the Clock Divider's internal counter is reset to the value specified with the Asynchronous Count attribute.

Connections: If you specify the Asynchronous Control pin, you can assign a value to the Asynchronous Value attribute. By default, the Asynchronous Value is assigned a value of zero if it is not specified. The Asynchronous Value attribute may also be specified to define the accumulator register's power-on value.

Whenever the Synchronous Control and Clock Enable inputs are High, the Clock Divider's internal counter is reset to the value specified with the Synchronous Count attribute on the next active clock transition.

Connections: If you specify the Synchronous Control pin and do not assign a value to the Synchronous Value attribute, the default value is the first count in the LFSR count sequence and a warning is issued.

When the Clock Enable input is High, the Clock Divider's internal counter increments on the next active Clock transition. When the Clock Enable is Low, the Clock Divider is unaffected by the Clock.

Connections: Clock Enable is optional. Use this input when you need to disable the clock temporarily. If you do not use the Clock Enable input, the Clock is always enabled.

If the Clock Enable input is High, the rising clock edge increments the Clock Divider's internal counter. The falling (negative) clock edge can be used by connecting an inverter to the Clock input.

Connections: The Clock pin is always specified.

Output Pins

The Clock Output port produces a pulse train whose period is a multiple of the period of the Clock input. The Clock Output has a 50 percent duty cycle except when the Clock Divisor attribute is assigned an odd number, in which case the Clock Output is Low for one extra Clock period. Alternatively, the duty cycle can be controlled with the Output Duty Cycle attribute.

Connections: The Clock Output pin is always specified.

Attributes

The Clock Divisor attribute specifies the number of input Clock cycles for each Output Clock Cycle. This value must be a positive integer.

Usage: The Clock Divisor can be set to a value of 2 or higher. A value must be specified for this parameter.

The Output Duty Cycle attribute defines the High time of the output clock wave form in terms of multiples of the input clock period. This value is an integer that is less than the Clock Divisor value. If Output Duty Cycle is not specified, a value of one-half the Clock Divisor value is used. If Clock Divisor is odd and Output Duty Cycle is not specified, the duty cycle is less than 50 percent because the output is High for only (n-1)/2 input clock periods.

Usage: Output Duty Cycle can be set to 1 or more but must be less than the value assigned to the Clock Divisor attribute.

The value of the Asynchronous Count attribute defines the power-on contents of the register. It also defines the value to which the register returns on assertion of the Asynchronous Control pin.

Usage: Asynchronous Count specifies the point in the Clock Divider's count sequence to which the internal LFSR counter returns on assertion of Asynchronous Control. For example, Asynchronous Count=0 causes the LFSR counter to return to the first count in its sequence.

The Synchronous Count attribute defines the value to which the register returns on assertion of the Synchronous Control pin.

Usage: Synchronous Count is available only if you specify the Synchronous Control pin. The Synchronous Count attribute specifies the point in the Clock Divider's count sequence to which the internal LFSR counter returns on assertion of Synchronous Control. For example, Synchronous Count=0 causes the LFSR counter to return to the first count in its sequence.