DATA REGISTER

The Data Register module is used to capture the data applied to its D_IN port on active Clock transitions. The contents of the data register are always present on the Q_OUT port. The module is synthesized as an array of flip-flops that can be loaded with predefined asynchronous and synchronous data.

Figure 4.10 The Data Register Module

Table 4_5 Data Register Truth Table

D_IN	Sync. Control	Clock Enable	Clock	Async. Control	Q_OUT
X	X	X	X	H	ASYNC_VAL
X	X	L		L	Q_OUTprev
X	H	H		L	SYNC_VAL
data	L	H		L	data

Input Pins

The data applied to the D_IN input port is loaded into the register when the Clock Enable is High and an active Clock transition occurs on the Clock pin.

Connections: The D_IN port is always specified.

The Asynchronous Control input is a level-sensitive input. When this input is High, it loads the value assigned to the Asynchronous Value attribute into the data register independently of the Clock and Clock Enable.

Connections: If you specify the Asynchronous Control pin, you can assign a value to the Asynchronous Value attribute. By default, the Asynchronous Value is assigned a value of zero if it is not specified. The Asynchronous Value attribute may also be specified to define the accumulator register's power-on value.

Synchronous Control is optional. Whenever the Synchronous Control and Clock Enable inputs are High, the value assigned to the Synchronous Value attribute is loaded into the data register on the next active clock transition. This input has priority over the Clock Enable input if both pins are High at the same time.

Connections: If you specify the Synchronous Control pin, you must assign a value to the Synchronous Value attribute.

When the Clock Enable input is High, the D_IN input data or the value assigned to the Synchronous Value attribute is loaded into the register on the next active Clock transition. When the Clock Enable is Low, the register contents are unaffected by the Clock. This input does not affect asynchronous load operations, which occur when the Asynchronous Control pin is asserted.

Connections: Clock Enable is optional. Use this input when you need to disable the clock temporarily. If you do not use the Clock Enable input, the Clock is always enabled. When the Style attribute is set to Latches, this input becomes a Gate Enable.

If the Clock Enable input is High, the rising clock edge loads the selected data into the register. You can implement an active falling (negative) clock edge by connecting an inverter to the Clock input.

Connections: The Clock pin is always specified. When the Style attribute is set to Latches, this input becomes a Gate.

Output Pins

Q_OUT always reflects the Data Register's contents.

Connections: Q_OUT is always specified.

Attributes

Style defines whether the module is implemented as an array of Latches or D-Type flip-flops.

Usage: Set this attribute to D-Type or Latches. The value D-Type is valid for all architectures. The value Latches is only valid for the XC4000EX and XC5200 device families.

The value of the Asynchronous Value attribute defines the power-on contents of the register. It also defines the value to which the register returns on assertion of the Asynchronous Control pin.

Usage: Asynchronous Value is always available. You can define it whether or not you use the Asynchronous Control pin. If you do not specify a value, the default value is zero.

The Synchronous Value attribute defines the value to which the register returns on assertion of the Synchronous Control pin.

Usage: Synchronous Value is available only if you specify the Synchronous Control pin.

The Use RPMs attribute determines whether the data flip-flops in the register maintain a constant relative location to each other. This attribute applies to the XC4000 and XC5200 device families only.

Usage: Use RPMs can be set to True or False. The default is False.