SRL16

16-Bit Shift Register Look-Up-Table (LUT)

SRL16 is a shift register look up table (LUT). The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length or dynamically adjusted.

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition and appears on the Q output. During subsequent Low-to-High clock transitions data is shifted to the next highest bit position as new data is loaded into Q.

Static Length Mode

To get a fixed length shift register, drive the A3 through A0 inputs with static values. The length of the shift register can vary from 1 bit to 16 bits as determined from the following formula:

Length = (8*A3) +(4*A2) + (2*A1) + A0 +1

If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. If they are all ones (1111), it is 16 bits long.

Dynamic Length Mode

The length of the shift register can be changed dynamically by changing the values driving the A3 through A0 inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), the length of the shift register changes from 16 bits to 8 bits.

Internally, the length of the shift register is always 16 bits and the input lines A3 through A0 select which of the 16 bits reach the output.

Inputs				Output
CLK	D	<SR(1)>	<SR(i)>	Q
1	X	No Chg	No Chg	No Chg
0	X	No Chg	No Chg	No Chg
	D	D	SR(i-1)	SR(L)
SR(1) = contents of first shift register SR(i) = contents of the i'th shift register stage (2<= n <= L) L = shift register length (1 through 16 determined by (8*A3) +(4*A2) + (2*A1) + A0 +1)