X74_162

4-Bit BCD Counter with Parallel and Trickle Enables, Active-Low Load Enable, and Synchronous Reset

X74_162 is a 4-stage, 4-bit, synchronous, loadable, resettable, cascadable binary-coded decimal (BCD) counter. The active-Low synchronous reset (R), when Low, overrides all other inputs and resets the data (QD, QC, QB, QA) and ripple carry-out (RCO) outputs Low during the Low-to-High clock (CK) transition. When the active-Low load enable input (LOAD) is Low and R is High, parallel clock enable (ENP) and trickle clock enable (ENT) are overridden and data on inputs A, B, C, and D is loaded into the counter during the Low-to-High clock transition. The data outputs (QD, QC, QB, QA) increment when ENP, ENT, LOAD, and R are High during the Low-to-High clock transition. The counter ignores clock transitions when ENP or ENT are Low and LOAD is High. RCO is High when QD, QA, and ENT are High and QC and QB are Low.

The carry-lookahead design accommodates cascading large counters without extra gating. Refer to “Carry-Lookahead Design” in the “X74_160” section for more information.

Inputs						Outputs
R	LOAD	ENP	ENT	D - A	CK	QD - QA	RCO
0	X	X	X	X		0	0
1	0	X	X	D - A		d - a	RCO
1	1	0	X	X	X	No Chg	RCO
1	1	X	0	X	X	No Chg	0
1	1	1	1	X		Inc	RCO
RCO = (QD•!QC•!QB•QA•ENT) d - a = state of referenced input one setup time prior to active clock transition

Figure 11.21 X74_162 Implementation XC3000, XC4000, XC5200, Spartans

Figure 11.22 X74_162 Implementation XC9000