X74_164

8-Bit Serial-In Parallel-Out Shift Register with Active-Low Asynchronous Clear

X74_164 is an 8-bit, serial input (A and B), parallel output (QH - QA) shift register with an active-Low asynchronous clear (CLR) input. The asynchronous CLR, when Low, overrides the clock input and sets the data outputs (QH - QA) Low. When CLR is High, the AND function of the two data inputs (A and B) is loaded into the first bit of the shift register during the Low-to-High clock (CK) transition and appears on the QA output. During subsequent Low-to-High clock transitions, with CLR High, the data is shifted to the next-highest bit position as new data is loaded into QA (A and BQA, QAQB, QBQC, and so forth).

Registers can be cascaded by connecting the QH output of one stage to the A input of the next stage, by tying B High, and by connecting the clock and CLR inputs in parallel.

Inputs				Outputs
CLR	A	B	CK	QA	QB - QH
0	X	X	X	0	0
1	1	1		1	qA - qG
1	0	X		0	qA - qG
1	X	0		0	qA - qG
qA - qG = state of referenced output one setup time prior to active clock transition

Figure 11.25 X74_164 Implementation XC3000, XC4000, XC5200, XC9000, Spartans