Previous

X74_377

8-Bit Data Register with Active-Low Clock Enable

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
Spartan
Virtex
Macro
Macro
Macro
Macro
Macro
Macro
Macro
N/A

figures/x4188n.gif

When the active-Low clock enable (G) is Low, the data on the eight data inputs (D8 - D1) is transferred to the corresponding data outputs (Q8 - Q1) during the Low-to-High clock (CK) transition. The register ignores clock transitions when G is High.

Inputs
Outputs
G
D8 - D1
CK
Q8 - Q1
1
X
X
No Chg
0
D8 - D1

d8 - d1
dn = state of referenced input one setup time prior to active clock transition

Figure 11.41 X74_377 Implementation XC3000, XC4000, XC5200, XC9000, Spartans

Next