This section gives an overview of attributes, constraints, and carry logic.
Attributes are instructions placed on symbols or nets in an FPGA or CPLD schematic to indicate their placement, implementation, naming, directionality, and so forth. This information is used by the design implementation software during placement and routing of a design. All the attributes listed in this chapter are available in the schematic entry tools directly supported by Xilinx unless otherwise noted, but some may not be available in textual entry methods such as VHDL.
Attributes applicable only to a certain schematic entry tool are described in the documentation for that tool. For third-party interfaces, consult the interface user guides for information on which attributes are available and how they are used.
Refer to the “Schematic Syntax” section in this chapter for guidelines on placing attributes on symbols on a schematic.
Constraints, which are a type, or subset, of attributes, indicate where an element should be placed.
Constraints that are attached to elements in the design prior to mapping are referred to as logical constraints. Applying logical constraints helps you to adapt your design's performance to expected worst-case conditions. Later, when you choose a specific Xilinx architecture and place and route your design, the logical constraints are converted into physical constraints.
You can attach logical constraints using attributes in the input design, which are written into the Netlist Constraints File (NCF), or with a User Constraints File (UCF). Refer to the “UCF/NCF File Syntax” section for the rules for entering constraints in a UCF or NCF file.
Three categories of logical constraints are described in detail in the “Attributes/Logical Constraints” section: placement constraints, relative location constraints, and timing constraints.
The “Placement Constraints” section gives examples showing how to place constraints on the various types of logic elements in FPGA designs.
For FPGAs, relative location constraints (RLOCs) group logic elements into discrete sets and allow you to define the location of any element within the set relative to other elements in the set, regardless of eventual placement in the overall design. Refer to the “Relative Location (RLOC) Constraints” section for detailed information on RLOCs.
Timing constraints allow you to specify the maximum allowable delay or skew on any given set of paths or nets in your design. Refer to the “Timing Constraints” section for detailed information on using timing constraints in a UCF file.
Constraints can also be attached to the elements in the physical design, that is, the design after mapping has been performed. These constraints are referred to as physical constraints and are defined in the Physical Constraints File (PCF), which is created during mapping. See the “Physical Constraints” section.
It is preferable to place any user-generated constraint in the UCF file - not in an NCF or PCF file.
Dedicated fast carry logic increases the efficiency and performance of adders, subtracters, accumulators, comparators, and counters. See the “Carry Logic in XC4000 and Spartans” section, “Carry Logic in XC5200” section, and “Carry Logic in Virtex” section at the end of this chapter.
