BUFG

Global Clock Buffer

BUFG, an architecture-independent global buffer, distributes high fan-out clock signals throughout a PLD device. The Xilinx implementation software converts each BUFG to an appropriate type of global buffer for the target PLD device.

For XC9000 designs, consult the device data sheet for the number of available global pins.

For an XC3000 design, you can use a maximum of two BUFG symbols (assuming that no specific GCLK or ACLK buffer is specified). For an XC4000 or Spartan series design, you can use a maximum of eight BUFG symbols (assuming that no specific BUFGP or BUFGS buffers are specified). For XC3000 designs, MAP always selects an ACLK, then a GCLK. For XC4000 or Spartan series designs, it always selects a BUFGS before a BUFGP. If you want to use a specific type of buffer, instantiate it manually.

To use a BUFG in a schematic, connect the input of the BUFG symbol to the clock source. Depending on the target PLD family, the clock source can be an external PAD symbol, an IBUF symbol, or internal logic. In Virtex, the BUFG cannot be driven directly from a pad; it can be driven from an IBUFG instead. For a negative-edge clock input, insert an INV (inverter) symbol between the BUFG output and the clock input. The inversion is implemented at the Configurable Logic Block (CLB) or Input Output Block (IOB) clock pin.

For XC9000 designs, BUFG is always implemented using an IOB. Connect the input of BUFG to an IPAD or an IOPAD that represents an external signal source. Each BUFG can drive any number of register clocks in a designs.

For XC9000 designs, the output of a BUFG may also be used as an ordinary input signal to other logic elsewhere in the design.