| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Virtex |
|---|---|---|---|---|---|---|---|
| Macro | Macro | Macro | Macro | Macro | Macro | Macro | Macro |
When the ADD input is High, ADSU4, ADSU8, and ADSU16 add two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow (OFL). ADSU4 adds two 4-bit words (A3 - A0 and B3 - B0) and a CI, producing a 4-bit sum output (S3 - S0) and CO or OFL. ADSU8 adds two 8-bit words (A7 - A0 and B7 - B0) and a CI producing, an 8-bit sum output (S7 - S0) and CO or OFL. ADSU16 adds two 16-bit words (A15 - A0 and B15 - B0) and a CI, producing a 16-bit sum output (S15 - S0) and CO or OFL.
When the ADD input is Low, ADSU4, ADSU8, and ADSU16 subtract Bz - B0 from Az- A0, producing a difference output and CO or OFL. ADSU4 subtracts B3 - B0 from A3 - A0, producing a 4-bit difference (S3 - S0) and CO or OFL. ADSU8 subtracts B7 - B0 from A7 - A0, producing an 8-bit difference (S7 - S0) and CO or OFL. ADSU16 subtracts B15 - B0 from A15 - A0, producing a 16-bit difference (S15 - S0) and CO or OFL.
In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low. OFL is active-High in add and subtract modes.
ADSU4, ADSU8, and ADU16 are implemented in the XC4000 and Spartans using carry logic and relative location constraints, which assure most efficient logic placement.
ADSU4, ADSU8, and ADSU16 CI and CO pins do not use the CPLD carry chain.
ADSU4, ADSU8, ADSU16 can operate, respectively, on either 4-, 8-, 16-bit unsigned binary numbers or 4-, 8-, 16-bit twos-complement numbers. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputs are interpreted as twos complement, the output can be interpreted as twos complement. The only functional difference between an unsigned binary operation and a twos-complement operation is how they determine when “overflow” occurs. Unsigned binary uses CO, while twos complement uses OFL to determine when “overflow” occurs.
With adder/subtracters, either unsigned binary or twos-complement operations cause an overflow. If the result crosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-out boundary, a carry-out is generated. The following figure shows the ADSU carry-out and overflow boundaries.
Figure 3.16 ADSU Carry-Out and Overflow Boundaries |  |
For unsigned binary operation, ADSU4 can represent numbers between 0 and 15, inclusive; ADSU8 between 0 and 255, inclusive; ADSU16 between 0 and 65535, inclusive. In add mode, CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is an active-Low borrow-out and goes Low when the difference exceeds the bounds.
An unsigned binary “overflow” that is always active-High can be generated by gating the ADD signal and CO as follows.
unsigned overflow = CO XNOR ADD
OFL is ignored in unsigned binary operation.
For twos-complement operation, ADSU4 can represent numbers between -8 and +7, inclusive; ADSU8 between -128 and +127, inclusive; ADSU16 between -32768 and +32767, inclusive. If an addition or subtraction operation result exceeds this range, the OFL output goes High.
CO is ignored in twos-complement operation.
This is the ADSU4 (4-bit), ADSU8 (8-bit), and ADSU16 (16-bit) topology for XC4000 and Spartan series devices.
This is the ADSU8 (8-bit) and ADSU16 (16-bit) topology for XC5200 devices.
Figure 3.17 ADSU8 Implementation XC3000 | |
Figure 3.18 ADSU8 Implementation XC4000, Spartans | |
Figure 3.19 ADSU8 Implementation XC5200 | |
Figure 3.20 ADSU8 Implementation Virtex | |
Figure 3.21 ADSU4 Implementation XC9000 | |
Figure 3.22 ADSU8 Implementation XC9000 | |
