CB2CLE, CB4CLE, CB8CLE, CB16CLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear

CB2CLE, CB4CLE, CB8CLE, and CB16CLE are, respectively, 2-, 4-, 8-, and 16-bit (stage) synchronously loadable, asynchronously clearable, cascadable binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock transition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High.

Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(t_CE-TC), where n is the number of stages and the time t_CE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not.

The counter is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs					Outputs
CLR	L	CE	C	Dz - D0	Qz - Q0	TC	CEO
1	X	X	X	X	0	0	0
0	1	X		Dn	dn	TC	CEO
0	0	0	X	X	No Chg	No Chg	0
0	0	1		X	Inc	TC	CEO
z= 1 for CB2CLE; z = 3 for CB4CLE; z = 7 for CB8CLE; z = 15 for CB16CLE dn = state of referenced input (Dn) one setup time prior to active clock transition. TC = Qz•Q(z-1)•Q(z-2)•...•Q0 CEO = TC•CE

Figure 4.4 CB8CLE Implementation XC3000

Figure 4.5 CB8CLE Implementation XC4000, XC5200, Spartans, Virtex

Figure 4.6 CB2CLE Implementation XC9000

Figure 4.7 CB8CLE Implementation XC9000