| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Virtex |
|---|---|---|---|---|---|---|---|
| Macro | Macro | Macro | Macro | Macro | Macro | Macro | Primitive |
FD is a single D-type flip-flop with data input (D) and data output (Q). The data on the D inputs is loaded into the flip-flop during the Low-to-High clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
Refer to the “FD4, 8, 16” section for information on multiple D flip-flops for the XC9000.
| Inputs | Outputs | |
|---|---|---|
| D | C | Q |
| 0 |  | 0 |
| 1 | | 1 |
Figure 5.4 FD Implementation XC3000, XC4000, XC5200, Spartans |  |
Figure 5.5 FD Implementation XC9000 | |
