FTSRLE

Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset

FTSRLE is a toggle/loadable flip-flop with toggle and clock enable and synchronous set and reset. The synchronous set input (S), when High, overrides all other inputs and sets data output (Q) High. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, clock enable input (CE) is overridden and output Q is reset Low. When load enable input (L) is High and S and R are Low, CE is overridden and data on data input (D) is loaded into the flip-flop during the Low-to-High clock transition. When the toggle enable input (T) and CE are High and S, R, and L are Low, output Q toggles, or changes state, during the Low-to- High clock transition. When CE is Low, clock transitions are ignored.

For FPGAs, the flip-flop is asynchronously cleared, output Low, when global reset (GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The GR/GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol. For CPLDs, the flip-flop is asynchronously preset when a High-level pulse is applied on the PRLD global net.

Inputs							Outputs
S	R	L	CE	T	D	C	Q
1	0	X	X	X	X		1
0	1	X	X	X	X		0
0	0	1	X	X	1		1
0	0	1	X	X	0		0
0	0	0	0	X	X	X	No Chg
0	0	0	1	0	X	X	No Chg
0	0	0	1	1	X		Toggle

Figure 5.71 FTSRLE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

Figure 5.72 FTSRLE Implementation XC9000