| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Virtex |
|---|---|---|---|---|---|---|---|
| N/A | Macro | Macro | N/A | N/A | Macro | Macro | Macro |
ILDI is a transparent data latch, which can hold transient data entering a chip. When the gate input (G) is High, data on the input (D) appears on the output (Q). Data on the D input during the High-to-Low G transition is stored in the latch.
The latch is asynchronously preset, output High, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans) default to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.
The ILDI is actually the input flip-flop master latch. It is possible to access two different outputs from the input flip-flop: one that responds to the level of the clock signal and another that responds to an edge of the clock signal. When using both outputs from the same input flip-flop, a transparent High latch (ILDI) corresponds to a falling edge-triggered flip-flop (IFDI_1). Similarly, a transparent Low latch (ILDI_1) corresponds to a rising edge-triggered flip-flop (IFDI).
Refer to the following figure for legal IFDI, IFDI_1, ILDI, and ILDI_1 combinations.
Figure 6.30 Legal Combinations of IFDI and ILDI for a Single IOB in XC4000 and Spartans |  |
| Inputs | Outputs | |
|---|---|---|
| G | D | Q |
| 1 | 1 | 1 |
| 1 | 0 | 0 |
| 0 | X | d |
| d = state of referenced input one setup time prior to High-to-Low gate transition | ||
Figure 6.31 ILDI Implementation XC4000, Spartans | |
Figure 6.32 ILDI Implementation Virtex | |
