LDC_1

Transparent Data Latch with Asynchronous Clear and Inverted Gate

LDC_1 is a transparent data latch with asynchronous clear and inverted gate. When the asynchronous clear input (CLR) is High, it overrides the other inputs (D and G) and resets the data (Q) output Low. Q reflects the data (D) input while the gate enable (G) input and CLR are Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High.

The latch is asynchronously cleared with Low output when power is applied. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR (XC5200) and GSR (XC4000X, SpartanXL, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.

Inputs			Outputs
CLR	G	D	Q
1	X	X	0
0	0	0	0
0	0	1	1
0	1	X	No Chg
0		D	d
d = state of input one setup time prior to Low-to-High gate transition

Figure 7.9 LDC_1 Implementation XC4000X, SpartanXL

Figure 7.10 LDC_1 Implementation XC5200