OFDE_1
D Flip-Flop with Active-High Enable Output Buffer and Inverted Clock
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Virtex
|
|---|
Macro
| Macro
| Macro
| Macro
| N/A
| Macro
| Macro
| Macro
|
OFDE_1 and its output buffer are located in an input/output block (IOB) except for XC5200. The data output of the flip-flop (Q) is connected to the input of an output buffer or OBUFE. The output of the OBUFE is connected to an OPAD or an IOPAD. The data on the data input (D) is loaded into the flip-flop on the High-to-Low clock (C) transition. When the active-High enable input (E) is High, the data on the flip-flop output (Q) appears on the O output. When E is Low, the output is high impedance (Z state or Off).
The flip-flop is asynchronously cleared with Low output when power is applied. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
E
| D
| C
| O
|
|---|
0
| X
| X
| Z
|
1
| 1
| 
| 1
|
1
| 0
|
| 0
|
