When you create combinational logic functions, the software attempts to collapse as much of the logic as possible into the smallest number of CPLD macrocells. Combinational logic optimization performed by the synthesis tool are generally not essential to the efficiency or performance of the resulting CPLD implementation. The CPLD fitter automatically performs all essential optimizations.
Any combinational logic function bounded between device I/O pins and flip-flops is subject to complete or partial collapsing. Collapsing the logic improves the speed of the logic path and can also reduce the amount of logic resources (macrocells, p-terms and FastCONNECT inputs) required to implement the function.
The process of collapsing logic into other logic functions is called "logic optimization".
Multilevel Logic Optimization seeks to simplify the total number of logic expressions in a design, and then collapse the logic in order to meet user objectives such as density, speed and timespecs. This optimization targets CPLD architecture, making it possible to collapse to the macrocell limits, reduce levels of logic, and minimize the total number of pterms.
Multilevel Logic Optimization extracts combinational logic from your design. Combinational logic includes:
Multilevel Logic Optimization operates on combinational logic according to the following rules:
Multilevel Logic Optimization can be set from the Advanced tab of the Implementation Options template of the Design Manager as follows:
ImplementMultilevel Logic Optimization will operate when you run the fitter.
If you wish to disable multilevel logic optimization when running a design from the cpld command, use the option -nomlopt. If you do not specify this option, the fitter automatically uses multilevel logic optimization.
When a larger combinational logic function consisting of several levels of AND-OR logic is completely collapsed (flattened), the number of product terms required to implement the function may grow considerably. By default, the fitter limits the number of p-terms used as a result of collapsing to 20 when using the Optimize Speed template, or 90 when using the Optimize Density template. If the collapsing of a logic level results in a logic function consisting of more p-terms than the limit (after Boolean reduction), then the collapsing of that logic level is not performed and the function will be implemented using two or more levels of AND-OR logic.
The fitter will not exceed the collapsing p-term limit even if a timing constraint applied to a path cannot be met.
When the Timing Optimization option is off, as it is in the Optimize Density template, the fitter only performs collapsing on a node if the total number of p-terms used after collapsing would be less than the total number of p-terms used by the combined functions before collapsing.
The overall extent to which logic is collapsed throughout an XC9000 design can be controlled from the Advanced Optimization tab of the Implementation Options template.
ImplementTo change the Pterm limit from Unix, use the "-pterms" parameter on the cpld command line:
cpld -pterms nn design_name
where nn is the maximum allowable number of p-terms that can be used to implement a logic function after collapsing. The allowable range for the pterms parameter is between 2 and 90.
If you find that the path delay of a larger, multi-level logic function in an XC9000 design is not satisfactory, try increasing the pterms parameter to allow the larger functions to be flattened further. For example, you may try increasing the p-term limit to 35 when rerunning the fitter, as shown:
cpld -pterms 35 design1
The fitter report (design_name.rpt) indicates the number of p-terms used for each logic function. You should see these numbers increase as you raise the pterms limit, until the design is fully flattened. At the same time, you'll see the internal combinational nodes eliminated until none remain.
Flattening typically increases the overall amount of p-term resources required to implement the design. Some designs which fit the target device initially may fail to fit if flattened too much. Other designs can be flattened completely and still fit. If you cannot increase the cpld pterms parameter enough to sufficiently flatten a critical path and still fit the target device, you may try applying logic optimization control at specific nodes in your design.
A special cell is provided in the XC9000 libraries, named KEEP, which is used to apply a logic optimization constraint to any signal passed through it. The KEEP cell has one input port named I and one output port named O (letter O). By instantiating a KEEP cell and passing through it a signal in the middle of a combinational logic function, you can prevent that signal from being collapsed.That is, you prevent the cell that drives the signal from being collapsed forward into any of its fanouts. The KEEP cell is instantiated as follows:
label: KEEP port map (O => outgoing_signal, I => incoming_signal);
In the following example, a KEEP cell is used to prevent the logic for an address decoder from being collapsed into the select input of a 16-bit multiplexer:
component KEEP port (O: out std_logic, I : in std_logic);
end component;
...
DECODE1 <= `1' when (ADDR_BUS = ADDR_1) else `0';
DATA_BUS <= A_BUS(0 to 15) when (DECODE1_NEW='1') else B_BUS;
U1: KEEP port map (O=>DECODE1_NEW,I=>DECODE1);By preventing logic optimization, the fitter will not attempt to duplicate the logic of the address decoder in each bit of the multiplexer.
You can use KEEP to break logic chains in non-speed-critical paths and prevent those functions from using too many p-terms. If you set the pterms parameter too high and your design no longer fits, try using KEEP to reduce the size of selected non-critical paths.
