Loading the Design into the Viewlogic Simulator

Checking the Invoke Simulator when Finished checkbox when you create the VSM file cause the Viewlogic simulator to automatically open. Otherwise, to open the Viewlogic simulation environment, click on the ViewSim icon shown in the following figure.

If your design contains LogiBLOX elements with VHDL models, you must use the Speedwave simulator. Click on the Speedwave icon shown in the next figure. This simulator requires an extended license to use.

Another option for designs containing VHDL models involves using Digital Fusion. Click on the Digital Fusion icon shown in the following figure. This also requires an extended license.

Digital Fusion is the top-level wrapper that incorporates the Viewlogic Digital Simulation Tools. The tools applicable to Xilinx designs are ViewSim, a gate-level simulation tool, and Speedwave, a gate-level and VHDL simulation tool. These tools, along with VCS, a Verilog simulation tool, and the analog simulation tools, comprise the Viewlogic Integrated Simulation Environment (ISE). These programs provide a common user interface and set of commands for any simulation flow.

To load a VSM file into any of the Viewlogic simulation tools, select File Load ViewSim Netlist. Navigate to your project directory and select func_sim.vsm.

Loading XMM Files

If the design contains RAM elements, and if the target family supports initial values on RAM, the flow described in the “Functionally Simulating Category A Designs” section generates a command file with the .xmm extension. Use this command file in the Viewlogic simulator. The file contains LOADM commands for each Viewsim RAM built-in primitive in the design.

To initialize the RAMs, execute the .xmm file from the Viewlogic simulator prompt by entering the following.

execute func_sim.xmm

You can include this statement in your design command file so that the initial contents load automatically. The Viewlogic simulator's restart command clears the RAM contents, so if you issue a restart in your command file, execute the .xmm file after that.

Executing Global Reset

After loading the design into the simulation environment and initializing the RAM/ROM components and external signals, you need to execute a global set/reset (GSR) command. This mimics the startup sequence of the FPGA or CPLD that you are simulating.

For example, for an XC4000 series device, run the following commands.

h GSR

sim 1000

l GSR

The names and polarities of the GSR signals appear in the following table.

Table 4_1 Global Set/Reset Signals

Annotating Values to the Original Schematic

Normally, node values calculated in the simulator annotate automatically to the Viewdraw schematic of the same name.

However, because you gave the name func_sim to your functional simulation netlist, the VSM file created has a different name than the original schematic. (to avoid conflicts with the original EDIF and WIR files). You must explicitly tell the simulator to annotate values to the original schematic, using the following command from the Viewlogic simulator.

schemnam <design>

The parameter <design> is the top-level schematic name. Values should then appear in the Viewdraw window.