HDL with Underlying Netlists

If your design includes underlying netlists (XNF or EDIF), the design must first be “translated” with the Xilinx Implementation tools in order to merge these additional netlists. Follow the steps below to successfully combine all of the individual modules into one netlist for simulation by “translating” the design in the Xilinx Implementation tools.

From the Project Manager, select Project Create Version. The Synthesis/Implementation dialog appears. The new version is given the default name shown in the Version Name box unless you change it. Click OK and the new version is created.
From the Project Manager, select Project Create Revision. The New Revision dialog appears. The new revision is given the default name shown in the Name box unless you change it. Click OK and the new revision is added to the newly created version from step 1.
From the Versions tab, right click on the newly created revision and select Invoke interactive Flow Engine.
From within the Flow Engine, select the Step button to translate the design.
After Translate is complete, go back to the Foundation Project Manager, and select Tools Simulation/Verification Checkpoint Gate Simulation Control.
Choose the appropriate NGD file from the Revision which was just created, and click OK. This invokes the simulator and loads the netlist.

For a description of how to select signals, choose stimulators, and run the simulation, refer to Steps 2 through 10 in the “Performing Functional Simulation (Optional)” section of the “Design Methodologies - HDL Flow” chapter.

Detailed information can also be found in the online help tutorial by selecting Help Foundation Help Contents. Then click on Logic Simulator. Double click on the Getting Started Tutorial. Another very detailed source can be found by selecting Help Foundation Help Contents. Click CPLD Design Flows. Scroll down and click The Functional Simulation Tutorial. You can also click Creating a New Test Vector File to find out detailed information about creating stimuli.