Setup Time°ú Hold Time ±×¸®°í Clock°úÀÇ °ü°è... |
ÀüÀÚ ¼³°è ¿£Áö´Ï¾îµéÀÌ ´ç¸éÇÏ´Â ¹®Á¦... |
- SETUP TIME °ú CLOCK - |
¸ðµç ³í¸®È¸·Î¿¡´Â ¼ø¼öÇÑ Á¶ÇÕȸ·Î¿Í ¼øÂ÷ȸ·Î ¹× ±â¾ïȸ·Î°¡ ÀÖ´Ù. ¿©±â¼ ¼øÂ÷ȸ·Î ¹× ±â¾ïȸ·ÎÀÇ °¡Àå ±âº»ÀÌ µÇ´Â Flip-FlopÀ» »ìÆ캸±â·Î ÇÑ´Ù.
Flip-FlopÀº ¿©·¯ Á¾·ù°¡ ÀÖÀ¸³ª ¿©±â¼´Â D-typeÀÇ Flip-FlopÀ» »ç¿ëÇÏ¿© ¾ê±â¸¦ Àü°³Çϱâ·Î ÇÏ°Ú´Ù. ¿ì¼± Flip-FlopÀº D ÀԷ´ÜÀÚ¿¡ µé¾î¿Â °ªÀÌ Ãâ·Â ´ÜÀÚÀÎ Q¿¡ Àü´ÞµÇ·Á¸é ¸î °¡Áö °í·Á»çÇ×ÀÌ ÃæÁ·µÇ¾î¾ß¸¸ µÈ´Ù.
¿ì¼±ÀûÀ¸·Î Clock´ÜÀÚ¸¦ »ìÆ캸¸é Positive-Edge¿¡¼ ¶Ç´Â Negative-Edge¿¡¼ µ¿ÀÛÇÏ´Â edge-trigger¹æ½Ä°ú CLOCK HIGH ¶Ç´Â CLOCK LOW¿¡¼ µ¿ÀÛÇÏ´Â level-trigger ¹æ½ÄÀÌ ÀÖ´Â µ¥ ¿©±â¼´Â edge-triggerÀ» ¿¹¸¦ µé±â·Î ÇÑ´Ù.
DÀԷ´ÜÀÚ´Â CLOCKÀÌ º¯ÈÇϱ⠼ö½Ã°£¾È¿¡ Àü¿¡ °ªÀÌ Á¤ÇØÁ® ÀÖ¾î¾ß ¿Ã¹Ù¸¥ ÀÔ·ÂÀÌ CLOCK¿¡ ¸ÂÃç Ãâ·Â Q¿¡ Àü´ÞÀÌ µÉ °ÍÀÌ´Ù. ÀÌ°ÍÀ» ÈçÈ÷ Setup TimeÀ̶ó ÇÑ´Ù. ¶ÇÇÑ CLOCKÀÌ º¯ÈÇÏ°í ¼ö½Ã°£¾È¿¡ D ÀÔ·Â °ªÀº º¯È¸¦ ÇÏÁö ¾Ê¾Æ¾ß ¿Ã¹Ù¸¥ ÀÔ·Â °ªÀÌ Ãâ·Â Q¿¡ Àü´ÞÀÌ µÉ °ÍÀÌ´Ù. ÀÌ°ÍÀ» ¿ì¸®´Â Hold TimeÀ̶ó ÇÑ´Ù.
¸¸ÀÏ SETUP TIME¹× HOLD TIMEÀ» ÃæºÐÈ÷ °í·ÁÇÏÁö ¾Ê°í ASIC¶Ç´Â PLD¸¦ ÀÌ¿ëÇÑ DIGITAL DESIGNÀ» ÇÏ·Á Çϸé ÃÖ°íÀÇ PERFORMANCEÀ» ³»Áö ¸øÇÒ °ÍÀÌ´Ù.
- XILINXÀÇ FPGA, CPLD´Â
ÀԷ´ÜÀÚ¿Í Ãâ·Â´ÜÀÚ ±×¸®°í Ŭ·°´ÜÀÚ¿¡
TIMING CONSTRAINTSÀ» ÁÖ¾î¼ ¿øÇÏ´Â µ¿ÀÛÀ» ÇÒ ¼ö ÀÖµµ·Ï ÇÏ´Â
OPTIONµéÀÌ ÀÖ´Â µ¥ ÀÌÁ¦ºÎÅÍ À̸¦ ÀÚ¼¼È÷ »ìÆ캸±â·Î ÇÏ°Ú´Ù. -
XILINX FOUNDATION PROJECT MANAGERÀ» ±âµ¿ ½ÃÅ°¸é ¾Æ·¡¿Í °°Àº ±×¸²ÀÌ ³ª¿Â´Ù. ¿©±â¼ ¿ÞÂÊ »ó´Ü¿¡ ÇöÀç ¿¸° ¶Ç´Â »õ·Î ¸¸µç PROJECTÀÇ ³»¿ëÀÌ ³ª¿À´Â PROJECT BROWSER°¡ ÀÖ´Â µ¥, ÇöÀç »ç¿ëµÇ´Â LIBRARY, SCHEMATIC,README, UCFµîÀÌ º¸ÀÏ °ÍÀÌ´Ù.
À§ÀÇ ±×¸²¿¡¼ TRAINING.UCF FILEÀÌ ÇÏ´Â ¿ªÇÒÀº Å©°Ô µÎ °¡Áö·Î ³ª´ ¼ö ÀÖ´Ù. ù¹ø° ¿ªÇÒÀº TIMING CONSTRAINTSÀ» ÁÖ¾î¼ ¿øÇÏ´Â ¼º´ÉÀ» ±¸ÇöÇϵµ·Ï ÇÏ´Â °Í°ú µÎ ¹ø° ¿ªÇÒÀº ÀÔ,Ãâ·Â ÇÉÀÇ À§Ä¡ ÇÒ´ç ¹× CLBÀÇ ³»ºÎ À§Ä¡ ÇÒ´çÀ» Á¤ÀÇÇÏ´Â PLACEMENT CONSTRAINTS°¡ ÀÖ´Ù. ¿©±â¼´Â TIMING CONSTRAINTS¿¡ ¸ÂÃç »ìÆ캸±â·Î ÇÑ´Ù.
TIMING.UCFÀÇ ³»¿ëÀ» »ìÆ캸±â·Î ÇÏÀÚ.
# The user constraint file (UCF)
# This is UCF file template which includes examples.
# See manuals for detailed description of these and other constraints
# Both the "#" sign and "//" (double slash) are used
as comments in the UCF file.
NET CLK PERIOD = 20 NS;
NET MAY OFFSET = IN : 6ns : before : CLK_PD ;
À§ÀÇ Á¦ÇÑ»çÇ×À» °¡Áö°í¼ PLACE & ROUTEÀ» ½ÇÇàÇÏ´Â °ÍÀ» °¡Áö°í ¿ì¸®´Â ÀÌ°ÍÀ» Timing Driven Placement And Route¶ó ÇÑ´Ù. Place and Route°¡ ¼öÇàÀÌ µÇ°í ³ª¼ »ç¿ëÀÚ°¡ ÁØ Á¦ÇÑ»çÇ׿¡ ¸ÂÃç¼ Post-Route Timing ReportÀ» »Ì¾Æ º¸¸é ¾Æ·¡¿Í °°´Ù. À̸¦ »ìÆ캸±â·Î ÇÏÀÚ.
----- Timing Report ---------
======================================================================
Timing constraint: NET "CLK" PERIOD
= 20 nS HIGH 50.000 % ;
2 items analyzed, 0 timing errors detected.
Minimum period is 9.858ns.
----------------------------------------------------------------------
Slack: 10.142ns path JIM to JIM relative to
20.000ns delay constraint
Path JIM to JIM contains 2 levels of logic:
Path starting from Comp: CLB_R8C1.K (from CLK)
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
CLB_R8C1.YQ Tcko 3.700R JIM
TIM
CLB_R8C1.C3 net (fanout=1) 1.158R TIM
CLB_R8C1.K Thh1ck 5.000R JIM
$I2/$1I37_Hint
JIM
-------------------------------------------------
Total (8.700ns logic, 1.158ns route) 9.858ns (to CLK)
(88.3% logic, 11.7%% route)
À§ÀÇ ³»¿ëÀ» º¸¸é ¸ÕÀú »ç¿ëÀÚ°¡ Á¤ÀÇÇÑ constraint°¡ PCF(Physical Constraint File)·Î º¯È¯µÇ¾î º¸ÀÌ°í ÀÖ´Ù. CLK net¿¡ ¿¬°áµÈ Flip-Flop, RAM, LatchµîÀÌ 20nsÀÇ ÁÖ±â¾È¿¡¼ µ¿ÀÛÀ» ÇÏ´Â µ¥ Duty CycleÀº 50:50À¸·Î ÇÑ´Ù. 2°³ÀÇ Ç׸ñÀÌ ºÐ¼®µÇ¾ú°í 20nsÀ» ³Ñ´Â °ÍÀº Çϳªµµ ¾øÀ¸¸ç, ÃÖ¼ÒÇÑÀÇ ÁÖ±â´Â 9.858ns ÀÌ´Ù.
slackÀº ¿¹ÃøÇÑ °Í°ú ºÐ¼®µÈ °Í°úÀÇ Â÷À̸¦ ÀǹÌÇϸç 20ns - 9.858ns = 10.142ns°¡ µÈ´Ù.
JIM¿¡¼ JIMÀ¸·Î °¡´Â °æ·Î´Â 2´Ü°è LogicÀ» °¡Áö¸ç CLB_R8C1.K(from CLK)¿¡¼ ½ÃÀ۵Ǵ °æ·Î´Â
CLB_R8C1.YQ Tcko(Clock K to outputs Q) 3.7ns
CLB_R8C1.C3 net(fanout=1) TIM net·Î °¡´Â delay 1.158
CLB_R8C1.K Thh1ck(Setup time before clock K(C inputs via H1 through H))
5.0
±×·¯¹Ç·Î Àüü Áö¿¬½Ã°£Àº 3.7+1.158+5=9.858ÀÌ µÈ´Ù. ±× Áß¿¡¼ 88.3%´Â Logic Áö¿¬À̸ç 11.7%´Â RouteÁö¿¬ÀÌ´Ù.
¾Æ·¡¿¡ CLB_R8C1ÀÇ ³»ºÎ ±¸¼ºÀ» º¸¿© ÀÌÇظ¦ µ½µµ·Ï ÇÏ¿´´Ù.
----------------------------------------------------------------------
Slack: 12.785ns path MAY to JIM relative to
20.000ns delay constraint
Path MAY to JIM contains 2 levels of logic:
Path starting from Comp: P20.PAD
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
P20.I1 Tpid 3.000R MAY
MAY
TOM
CLB_R8C1.C4 net (fanout=1) 1.215R TOM
CLB_R8C1.K Tdick 3.000R JIM
TIM
-------------------------------------------------
Total (6.000ns logic, 1.215ns route) 7.215ns (to CLK)
(83.2% logic, 16.8%% route)
À§ÀÇ ³»¿ëÀº ÀÔ·Â Æе忡 ¿¬°áµÈ Flip-FlopÀÇ Áö¿¬½Ã°£À» º¸¿©ÁÖ°í ÀÖ´Ù. PIN20À» Åë°úÇÏ¿© °É¸®´Â ½Ã°£ÀÌ 3ns, CLB_R8C1.C4 PIN¿¡ ¿¬°áµÇ´Â Net delay°¡ 1.215ns, CLB_R8C1.K¿¡ °ü·ÃµÈ Setup Time before clock K (C inputs via DIN) 3ns, ±×·¯¹Ç·Î 3+1.215+3 = 7.215ns°¡ µÈ´Ù.
======================================================================
Timing constraint: COMP "MAY" OFFSET
= IN 6.000 nS BEFORE COMP "CLK_PD" ;
1 item analyzed, 0 timing errors detected.
Minimum allowable offset is 1.915ns.
----------------------------------------------------------------------
Slack: 4.085ns path MAY to JIM relative to
5.300ns delay constraint CLK_PD to JIM and
6.000ns offset MAY to CLK_PD
ÀÔ·Â MAY´Â CLK_PD°¡ µé¾î¿À±â Àü 6NSÀÇ Setup TimeÀÌ ÇÊ¿äÇϸç ÇÑ Ç׸ñÀÌ ºÐ¼®µÆÀ¸¸ç ¿¡·¯´Â ¾ø´Ù. Setup TimeÀ» 6nsÀ» Á¤ÀÇÇÏ¿´À¸¸ç minimum input arrival time before clk ÀÌ 1.915ns ÀÌ´Ù. ±×·¯¹Ç·Î SlackÀº 6ns - 1.915ns = 4.085nsÀ̸ç CLK_PD¼ JIM ±îÁö´Â 5.3ns delay constraintÀÌ°í MAY¿Í CLK_PD´Â 6ns offsetÀÌ´Ù.
Data path MAY to JIM contains 2 levels of logic:
Path starting from Comp: P20.PAD
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
P20.I1 Tpid 3.000R MAY
MAY
TOM
CLB_R8C1.C4 net (fanout=1) 1.215R TOM
CLB_R8C1.K Tdick 3.000R JIM
TIM
-------------------------------------------------
Total (6.000ns logic, 1.215ns route) 7.215ns (to CLK)
(83.2% logic, 16.8%% route)
Clock path CLK_PD to JIM contains 2 levels of logic:
Path starting from Comp: P35.PAD
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
P35.CLKIN Tclkin 0.000R CLK_PD
CLK_PD
BUFGP_BL.I net (fanout=1) 3.890R CLK_PD
BUFGP_BL.O Tclk 0.000R $I8
CLB_R8C1.K net (fanout=2) 1.410R CLK
-------------------------------------------------
Total (0.000ns logic, 5.300ns route) 5.300ns
(0.0% logic, 100.0%% route)
ÀÔ·Â MAY°¡ ÀÔ·Â Æе带 °ÅÃÄ TOMÀ̶ó´Â NET DELAYÀ» °®°í TOM NET¿¡ ¿¬°áµÈ Flip-FlopÀÇ D ÀԷ´ÜÀÚ¿¡ ¿¬°áµÉ ¶§ Setup timeÀ» Delay·Î °£ÁÖÇÏ¿© ÃÑ 7.215ns Delay¸¦ °¡Áö´Â µ¥ ¹ÝÇÏ¿©, CLK_PD´Â Àü¿ë CLOCK PADÀ» °ÅÃÄ CLK¿¡ ¿¬°áµÇ´Âµ¥ ¼ø¼öÇÑ Net Delay°¡ 5.3ns°¡ µÈ´Ù. ¿©±â¼ ¿ì¸®´Â ±âº»ÀûÀÎ ¹ýÄ¢À» »ó±â ½Ãų ÇÊ¿ä°¡ ÀÖ´Ù. Áï Data-In °ú Clock »çÀÌÀÇ Setup Time¹× Hold Time, Minimum Pulse WidthÀ» ±â¾ïÇÒ ÇÊ¿ä°¡ ÀÖ´Ù.
¸¸ÀÏ µ¿ÀÏÇÑ ½Ã°£ÀÎ 12½Ã Á¤°¢¿¡ Data¿Í ClockÀ» Àΰ¡Çϸé Data´Â 12½Ã 7.215nsÈÄ¿¡ D input¿¡ µµÂøÇÏ°í ClockÀº 12½Ã 5.3ns¿¡ µµÂøÇÏ´Â µ¥ ÀÌ·¸°Ô µÇ¸é °¡Àå ±âº»ÀûÀÎ Setup TimeÀ» ¸ÂÃßÁö ¸øÇÏ´Â °á°ú¸¦ ÃÊ·¡ÇÏ°Ô µÇ´Â °ÍÀÌ´Ù. ±×·¡¼ µé¾î¿À´Â ÀÔ·Â DataÀ» ÃÖ¼ÒÇÑ 7.215ns - 5.3ns = 1.915ns·Î CLOCK¿¡ ¾Õ¼ º¸³»¸é Á¤È®ÇÏ°Ô ¸Â´Â(Just In Time) Delay ¹× Setup time Á¶°ÇÀÌ ÁöÄÑÁö´Â °á°ú°¡ µÈ´Ù. Áï CLOCKº¸´Ù DataÀ» 1.915ns ¸ÕÀú º¸³»¸é ¹®Á¦°¡ ÇØ°áµÇ´Â °ÍÀÌ´Ù.
-1.915ns¿¡ Data°¡ µé¾î¿À°í 0ns¿¡ clockÀÌ µé¾î¿À¸é clockÀº 0+5.3ns = 5.3ns¿¡ Flip-FlopÀÇ Clock¿¡ µµ´ÞÇÏ°í Data´Â -1.915ns + 7.215ns = 5.3ns°¡ µÇ¾î ²Ë Â¥¸ÂÃá Setup TimeÀ» °¡Á® ÀÌ»ó ¾øÀÌ DataÀ» Àü¼ÛÇÒ °ÍÀÌ´Ù. ±×·¯¹Ç·Î minimum input arrival time before clock ÀÌ 1.915ns°¡ µÇ´Â °ÍÀÌ´Ù.
À§ÀÇ REPORT¿¡ MAY¿¡¼ TIM±îÁöÀÇ ÀÔ·Â PATH¿Í CLK_PD¼ CLK±îÁöÀÇ Àü¿ë CLOCK PATHÀÇ DELAY°¡ ÀÚ¼¼ÇÏ°Ô ±â¼úµÇ¾î ÀÖ´Ù. ¿©±â¼ OFFSETÀÇ »ç¿ë¹æ¹ýÀ» »ìÆ캸¸é ÀԷ°ú Ãâ·Â ÇÉ°ú CLOCK Àü¿ëÇÉ »çÀÌÀÇ °ü°è¸¦ ¼³¸íÇÏ°í ÀÖÀ¸¸ç system level¼ Á¢±ÙÇØ¾ß ÀÌÇØ°¡ ½¬¿ï ¼ö ÀÖ´Ù. CHIP1, CHIP2, CHIP3À» ÀÌ¿ëÇÏ¿© ½Ã½ºÅÛÀ» ¼³°è ½Ã CLOCKÀº µ¿ÀÏÇÑ °ÍÀ» »ç¿ëÇÏ¸ç µ¿±â½ÄÀ¸·Î ȸ·Î¸¦ ²Ù¹Î´Ù¸é ÃÖÀûÀÇ ¼º´ÉÀ» ¿øÇÑ´Ù¸é ÃÖ¼ÒÇÑ µÎ °¡Áö »çÇ×Àº °í·ÁÇØ¾ß ÇÒ °ÍÀÌ´Ù. ¸¸ÀÏ CHIP2À» XILINX FPGA·Î ¼³°èÇÑ´Ù¸é ù¹ø°·Î XILINX FPGAÀÇ Flip-FlopÀÇ ÀԷ¿¡ µµ´ÞÇÏ´Â ½Ã°£Àº ¾Ë¾Æ¾ß Flip-FlopÀÇ Setup Time¿¡ À§¹èµÇÁö ¾Ê°í ½Ã½ºÅÛ ¼³°è¸¦ ÇÒ ¼ö ÀÖÀ» °ÍÀÌ°í ÀÌ°ÍÀ» Timing ConstraintsÀ» ÀÌ¿ëÇØ ¾´´Ù¸é ¾Æ·¡¿Í °°À» °ÍÀÌ´Ù.
NET MAY OFFSET = IN 6NS BEFORE CLK_PD ;
µÎ ¹ø°·Î XILINX FPGAÀÇ Flip-FlopÀÇ Ãâ·Â ÇÉÀÌ ¿ÜºÎ¿¡ Àü´ÞµÇ´Â ½Ã°£ÀÌ ¾ó¸¶¸é CHIP3ÀÇ Setup-Time¿¡ À§¹èµÇÁö ¾Ê°í ÃÖÀûÀÇ ¼º´ÉÀ» ±¸ÃàÇÒ ¼ö ÀÖÀ»±î?
NET JOE OFFSET = OUT 6NS AFTER CLK_PD ;
----------------------------------------------------------------------
All constraints were met.
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 4 paths, 0 nets, and 4 connections (80.0% coverage)
Design statistics:
Minimum period: 9.858ns (Maximum frequency: 101.440MHz)
Minimum input arrival time before clock: 1.915ns
Analysis completed Wed Jul 01 16:00:27 1998
----------------------------------------------------------------------
¿©±â¼ ¿ì¸®´Â CONSTRAINT ÀÇ ÇüŸ¦ Á¶±Ý ¹Ù²Ù¾î¼ »ý°¢À» ÇØ º¸ÀÚ.
NET CLK OFFSET = IN 14NS AFTER CLK_PD;
À§ÀÇ ¹®ÀåÀº NET CLK OFFSET = IN 6 NS BEFORE CLK_PD;¿Í °°Àº °ÍÀÌ´Ù. ´Ù¸¸ ClockÀÇ 1ÁÖ±âÀÎ 20NS¿¡¼ Clock Àü´Ü¿¡¼ Çؼ®ÇÒ °ÍÀΰ¡, Clock ÈÄ´Ü¿¡¼ Çؼ®ÇÒ °ÍÀΰ¡ÀÇ ¹®Á¦ÀÌ´Ù.
======================================================================
Timing constraint: COMP "MAY" OFFSET = IN 14.000 nS AFTER
COMP "CLK_PD" ;
1 item analyzed, 0 timing errors detected.
Maximum allowable offset is 18.085ns.
----------------------------------------------------------------------
Slack: 4.085ns path MAY to JIM relative to
5.300ns delay constraint CLK_PD to JIM and
6.000ns offset MAY to CLK_PD
Data path MAY to JIM contains 2 levels of logic:
Path starting from Comp: P20.PAD
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
P20.I1 Tpid 3.000R MAY
MAY
TOM
CLB_R8C1.C4 net (fanout=1) 1.215R TOM
CLB_R8C1.K Tdick 3.000R JIM
TIM
-------------------------------------------------
Total (6.000ns logic, 1.215ns route) 7.215ns (to CLK)
(83.2% logic, 16.8%% route)
Clock path CLK_PD to JIM contains 2 levels of logic:
Path starting from Comp: P35.PAD
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
P35.CLKIN Tclkin 0.000R CLK_PD
CLK_PD
BUFGP_BL.I net (fanout=1) 3.890R CLK_PD
BUFGP_BL.O Tclk 0.000R $I8
CLB_R8C1.K net (fanout=2) 1.410R CLK
-------------------------------------------------
Total (0.000ns logic, 5.300ns route) 5.300ns
(0.0% logic, 100.0%% route)
----------------------------------------------------------------------
All constraints were met.
¿©±â¼ ¿ì¸®´Â ¶È°°Àº °á°ú¸¦ ¾ò¾úÀ¸¸ç Çؼ®»óÀÇ Â÷ÀÌÁ¡À» ÀÌÇØÇÏ¸é µÈ´Ù. ¿ì¼± ÀÔ·Â delay´Â 7.215NSÀ̸ç Clock delay´Â 5.3NS ÀÌ¸ç ±×Â÷ÀÌ´Â 1.915NS°¡ µÈ´Ù. Áï CLOCKÀÌ º¯Çϱâ Àü 1.915NS¾È¿¡ D inputÀÌ ¾ÈÁ¤µÇ¸é µÇ´Â °ÍÀ̸ç À̸¦ ´Þ¸® Ç¥ÇöÇϸé Ŭ·°ÀÌ º¯ÈÇÑ ÈÄ ÃÖ´ë 20NS-1.915NS = 18.085NS ¾È¿¡ ÀÔ·ÂÀÌ º¯ÇÏ¸é µÇ´Â °ÍÀÌ´Ù.
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 4 paths, 0 nets, and 4 connections (80.0% coverage)
Design statistics:
Minimum period: 9.858ns (Maximum frequency: 101.440MHz)
Maximum input arrival time after clock: 18.085ns
Minimum input arrival time before clock
: 1.915ns
¿ì¸° ¸î°¡Áö ¹ýÄ¢À» °¡Áö°í Çؼ®À» ÇÑ´Ù. ¸ÕÀú ÀÔ·ÂÀº CLOCKÀÌ º¯Çϱâ Àü BEFORE Áï MINIMUN INPUT ARRIVAL TIME BEFORE CLOCKÀ¸·Î Çؼ®À» ÇÑ´Ù.
ÀÌÁ¨ Ãâ·ÂÀ» ´Ù·ç±â·Î ÇÏÀÚ.
===========================================================================
Timing constraint: COMP "JOE" OFFSET
= OUT 6.000 nS AFTER COMP "CLK_PD" ;
1 item analyzed, 1 timing error detected.
Minimum allowable offset is 22.697ns.
---------------------------------------------------------------------------
Slack: -16.697ns path CLK_PD to JIM relative to
17.370ns delay constraint JIM to JOE and
6.000ns offset CLK_PD to JOE
CLOCK¿¡ ¸ÂÃç Ãâ·ÂÀÌ ³ª°¡´Â µ¥ ÇÊ¿äÇÑ ½Ã°£Àº ¸ÕÀú ClockÀÌ µµÂøÇÏ´Â µ¥ °É¸®´Â Áö¿¬½Ã°£°ú CLOCK TO OUT Áö¿¬½Ã°£°ú OUTPUT PADÀ» °ÅÄ¡´Â ½Ã°£ÀÇ ÇÕÀ̹ǷÎ, 5.327ns + 17.37ns = 22.697ns°¡ °É¸°´Ù. ±×·¯¹Ç·Î SlackÀº 6ns - 22.697ns = -16.697ns°¡ µÈ´Ù. Áï CLOCKÀÌ ÃµÀÌÇÑ ÈÄ ÃÖ¼ÒÇÑ 22.697ns°¡ °É·Á¾ß FPGA OUT PINÀ¸·Î Ãâ·ÂÀÌ Àü´ÞµÈ´Ù. ÀÌ Á¤º¸¸¦ °¡Áö°í ÀÌ Ãâ·ÂÀ» ´Ù¸¥ CHIPÀÇ ÀÔ·ÂÀ¸·Î »ç¿ë ½Ã ±×¸®°í °°Àº ClockÀ¸·Î µ¿±â ½Ãų½Ã ÃÖ¼ÒÇÑ 23NSÀÇ CLOCK Áֱ⸦ °¡Á®¾ß ÇÑ´Ù.
Clock path CLK_PD to JIM contains 2 levels of logic:
Path starting from Comp: P13.PAD
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
P13.CLKIN Tclkin 0.000R CLK_PD
CLK_PD
BUFGP_TL.I net (fanout=1) 3.955R CLK_PD
BUFGP_TL.O Tclk 0.000R $I8
CLB_R14C7.K net (fanout=2) 1.372R CLK
-------------------------------------------------
Total (0.000ns logic, 5.327ns route) 5.327ns
(0.0% logic, 100.0%% route)
Data path JIM to JOE contains 2 levels of logic:
Path starting from Comp: CLB_R14C7.K (from CLK)
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
CLB_R14C7.XQ Tcko 3.700R JIM
JIM
P39.O net (fanout=1) 1.670R JIM
P39.PAD Tops 12.000R JOE
JOE.OUTBUF
JOE
-------------------------------------------------
Total (15.700ns logic, 1.670ns route) 17.370ns
(90.4% logic, 9.6%% route)
---------------------------------------------------------------------------
1 constraint not met.
Timing summary:
---------------
Timing errors: 1 Score: 16697
Constraints cover 5 paths, 0 nets, and 5 connections (100.0% coverage)
Design statistics:
Minimum period: 9.828ns (Maximum frequency: 101.750MHz)
Minimum input arrival time before clock: 1.881ns
Minimum output required time after clock: 22.697ns
Ãâ·ÂÀº ClockÀÌ ÃµÀÌÇÑ Èĸ¦ ±âÁØÀ¸·Î °è»êÇÑ´Ù. Áï Minimum output required time after clockÀ» ÀÌ¿ëÇÑ´Ù.
Analysis completed Sun Jul 05 23:38:17 1998
---------------------------------------------------------------------------
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