IAS:
FPU Modeling

FPU Implementation Specific Issues for IAS

The structure of a IEEE-754 Single Precision and Double Precision Floating Point value is: (bit 0 = lsb)

Single Precision	Double Precision
bit 31: sign	bit 63: sign
bit 30-23: exponent	bit 62-52: exponent
bit 22-0: mantissa	bit 51-0: mantissa

Though picoJava-II implements IEEE-754 arithmetic, there are a few cases where the exact behavior is allowed by the standard to be implementation dependent. Even if the underlying architecture upon which IAS is running is IEEE compliant, IAS cannot rely entirely upon it to generate Floating Point results which match, bit for bit, to the picoJava-II FPU. It is improtant to match the RTL bit patterns exactly in IAS, since cosimulation does a bitwise compare between IAS and RTL state.

IAS contains special code to handle those special cases which are not defined precisely by the IEEE spec.

The special cases are defined here.

Any case not documented here is handled by the native Floating Point mechanism of the underlying architecture and is assumed to be IEEE compliant.

f2i/l, d2i/l	On a NaN input these instructions generate a result of 0.
f2d	On a NaN input, the output is a NaN with the following structure:         sign bit: 0         exponent: 0x7ff         mantissa: The 23 bits of the input mantissa are jammed into         the 23 msb's of the result mantissa.         The rest of the mantissa bits are zeroed.
d2f	On a NaN input, the output is always an INaN (*)
fadd, dadd, fmul, dmul, fdiv, ddiv, fsub, dsub, frem, drem	On an operation like A op B, if A is a NaN, A is copied exactly to the result,     except for the sign bit, which is reset. else if B is a NaN, B is copied exactly to the result,     except for the sign bit, which is reset. else if the operation results in a NaN value, the resultant     value is an INaN. else let the underlying architecture compute the value.     For frem or drem the value is to be calculated by     the C library function fmod, as     documented in the Java Virtual Machine Specification.
fneg, dneg	The sign bit is simply inverted, irrespective of the FP value.
fcmp*, dcmp*	Do not need any special handling.

Note: (*) INaN: for Single Precision, this is the pattern 0x7fff000
for Double Precision, this is the pattern 0x7fffe000 00000000