To simulate the picoJavaTM-II RTL core, you need a Verilog simulator such as Cadence's Verilog-XLTM or Synopsys's VCSTM. Though the design is likely to work correctly with other Verilog simulators, the picoJava-II core has been extensively tested only with these two simulators.
Before building the RTL model, you need to have set up your environment. These sections step you through the process of building a picoJava-II RTL model.
Configuring the core
Compiling custom Verilog-XL executable
Compiling custom vcs executable
Adding Signalscan and other 3rd party PLIs
The default configuration of the core is:
- 16KB I-Cache,
- 16KB D-Cache
- FPU present
If you need to change the configuration of the core, follow these instructions.
The custom Verilog executable for the picoJava-II environment is called
pj2vlog. The steps to compilepj2vlogare:
cdinto the$DSVHOMEdirectory.- Look at the
verilog/src/Makefile.in.
Verify that you have the correct libaries necessary for the version of Verilog-XL that you are using. The default settings here refer to Verilog-XL 2.3.3 from the 95.04 release. Other setting are given for various other versions that have been successfully compiled. For more information, go to Cadence Verilog-XL.- Type
make pj2vlog. This builds the custom executablepj2vlogin the$DSVHOME/bindirectory if everything builds correctly.- A quick way to check if you build pj2vlog correctly is to run some sample tests.
The custom VCS executable for the picoJava-II environment is called
pj2vcs. The steps to compilepj2vcsare:
cdinto the$DSVHOMEdirectory.- Verify that the command
vcsis in your search path.- Type
make pj2vcs. This builds the custom executablepj2vcsin the$DSVHOME/bindirectory
if everything builds correctly.- A quick way to check if you build pj2vcs correctly is to run some sample tests.
You can view graphical waveforms of the logic inside the picoJava-II core using the SignalscanTM tool from Design Automation. If you have access to Signalscan and would like to be able to use it, you need to add in support for Signalscan when building the custom RTL model.
Support for generating DAI's Signalscan database of the simulation is included in the picoJava-II testbench environment. By default, this support is not enabled.
To enable this feature, you must
define SIGNALSCANin$PICOJAVAHOME/$PROJECT/sim/env/sys.h.The steps to produce a Verilog/VCS executable, which includes the PLIs are:
Verilog-XL
cdinto$DSVHOME/verilog/src.- Modify
pj_user.cto add the new PLI functions.- Modify
Makefile.into include the PLI libraries in the EXTRA_LIB line.- Compile the executable as described above.
VCS
cdinto$DSVHOME/verilog/src.- Modify
vcs.tabto add the new PLI functions.- Modify
$DSVHOME/bin/vcscto include the PLI libraries in thevcscompile line.- Compile the executable as described above.
You can follow these steps for linking in any third-party (or even your own) PLI routines.