library IEEE; use IEEE.std_logic_1164.all; -- defines std_logic types entity jcounter is port ( clk : in STD_LOGIC; q : buffer STD_LOGIC_VECTOR (7 downto 0) ); end jcounter; architecture jcounter_arch of jcounter is begin process (CLK) begin if CLK'event and CLK='1' then -- CLK rising edge q(7 downto 1) <= q(6 downto 0); -- Shift lower bits q (0) <= not q(7); -- Circulate inverted MSB end if; end process; end jcounter_arch;