| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Virtex |
|---|---|---|---|---|---|---|---|
| N/A | Primitive | Primitive | N/A | N/A | Primitive | Primitive | Macro |
OFDXI is contained in an input/output block (IOB). The output (Q) of the D flip-flop is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flip-flop during the Low-to-High clock (C) transition and appears at the output (Q). When CE is Low, the output does not change.
The flip-flop is asynchronously preset with High output when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans) default to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.
| Inputs | Outputs | ||
|---|---|---|---|
| CE | D | C | Q |
| 1 | D |  | d |
| 0 | X | X | No Chg |
| d = state of referenced input one setup time prior to active clock transition | |||
Figure 8.44 OFDXI Implementation Virtex |  |
