Libraries GuideChapter 5: Design Elements (F5MAP to FTSRLE)
FDP_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Spartan2
| Virtex
|
|---|
N/A
| Macro
| Macro
| Macro
| N/A
| Macro
| Macro
| Primitive
| Primitive
|
FDP_1 is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and presets the Q output High. The data on the D input is loaded into the flip-flop when PRE is Low on the High-to-Low clock (C) transition.
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs simulate power-on when global reset (GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The active level of the GR/GSR defaults to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
PRE
| C
| D
| Q
|
|---|
1
| X
| X
| 1
|
0
| 
| 1
| 1
|
0
|
| 0
| 0
|
Figure 5.17 FDP_1 Implementation XC4000E, XC4000X, XC5200, Spartan, SpartanXL