Port Names

Some port expressions are identifiers. If the port expression is an identifier, the port name is the same as the identifier. A port expression is not an identifier if the expression is a single bit, a group of bits selected from a vector of bits, or a concatenation of signals. In these cases, the port is unnamed unless you explicitly name it.

The following example shows some module definition fragments that illustrate the use of port names. The ports for module ex1 are named a, b, and z, and are connected to nets a, b, and z, respectively. The first two ports of module ex2 are unnamed; the third port is named z. The ports are connected to nets a[1], a[0], and z, respectively. Module ex3 has two ports; the first port is unnamed and is connected to a concatenation of nets a and b; the second port, named z, is connected to net z.

module ex1(a,b,z);

   input a,b; 

   output z; 

endmodule 

module ex2(a[1],a[0],z); 

   input [1:0] a; 

   output z;

endmodule 

module ex3({a,b},z); 

   input a,b; 

   output z; 

endmodule

Renaming Ports

You can rename a port by explicitly assigning a name to a port expression with the dot (.) operator. The module definition fragments in the following example show how to rename ports. The ports for module ex4 are explicitly named in_a, in_b, and out and are connected to nets a, b, and z. Module ex5 shows ports named i1, i0, and z connected to nets a[1], a[0], and z, respectively. The first port for module ex6 (the concatenation of nets a and b) is named i.

module ex4(.in_a(a),.in_b(b),.out(z));

   input a,b;

   output z; 

endmodule 

module ex5(.i1(a[1]),.i0(a[0]),z); 

   input [1:0] a; 

   output z; 

endmodule 

module ex6(.i({a,b}),z); 

   input a,b; 

   output z;

endmodule