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In Verilog, the task statements are similar to functions except that task statements can have output and inout ports. You can use the task statement to structure your Verilog code so that a portion of code is reusable.
In Verilog, tasks can have timing controls and they can take a nonzero time to return. However, Foundation Express ignores all timing controls, so synthesis might disagree with simulation if the timing controls are critical to the function of the circuit.
The following example shows how a task statement is used to define an adder function.
module task_example (a, b, c);
input [7:0] a, b;
output [7:0] c;
reg [7:0] c;
task adder;
input [7:0] a, b;
output [7:0] adder;
reg c;
integer i;
begin
c = 0;
for (i = 0; i <= 7; i = i + 1) begin
adder[i] = a[i] ^ b[i] ^ c;
c = (a[i] & b[i]) | (a[i] & c) | (b[i] & c);
end
end
endtask
always
adder (a, b, c); // c is a reg
endmodule
Note: Only reg variables can receive output values from a task; wire variables cannot.