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The // synopsys state_vector directive labels a variable in a Verilog description as the state vector of an equivalent finite state machine.
The syntax for the state_vector directive is one of the following.
// synopsys state_vector vector_name
or
/* synopsys state_vector vector_name */
The vector_name variable is the name chosen as a state vector. This declaration allows Foundation Express to extract the labeled state vector from the Verilog description. Used with the enum directive, described in the next section, the state_vector directive allows you to define the state vector of a finite state machine (and its encodings) from a Verilog description. The following example shows one way to use the state_vector directive.
Warning: Do not define two state_vector directives in one module. Although Foundation Express does not issue an error message, it recognizes only the first state_vector directive and ignores the second.reg [1:0] state, next_state;
// synopsys state_vector state
ays @ (state or in) begin
case (state) // synopsys full_case
0: begin
out = 3;
next_state = 1;
end
1: begin
out = 2;
next_state = 2;
end
2: begin
out = 1;
next_state = 3;
end
3: begin
out = 0
if (in)
next_state = 0;
else
next_state = 3;
endcase
end
always @ (posedge clock)
state = next_state;