Don't Care Inference

You can greatly reduce circuit area by using don't care values. To use a don't care value in your design, create an enumerated type for the don't care value.

Don't care values are best used as default assignments to variables. You can assign a don't care value to a variable at the beginning of a module, in the default section of a case statement, or in the else section of an if statement.

Limitations of Using Don't Care Values

In some cases, using don't care values as default assignments can cause the following problems.

• Don't care values create a greater potential for mismatches between simulation and synthesis.
  
  
• Defaults for variables can hide mistakes in the Verilog code.
  
  For example, you might assign a default don't care value to VAR. If you later assign a value to VAR, expecting VAR to be a don't care value, you might have overlooked an intervening condition under which VAR is assigned.
  
  Therefore, when you assign a value to a variable (or signal) that contains a don't care value, make sure that the variable (or signal) is really a don't care value under those conditions. Note that assignment to an x is interpreted as a don't care value.
  
  

Differences Between Simulation and Synthesis

Don't care values are treated differently in simulation and in synthesis, and there can be a mismatch between the two. To a simulator, a don't care is a distinct value, different from a one or a zero. In synthesis, however, a don't care becomes a zero or a one (and hardware is built that treats the don't care value as either a zero or a one).

Whenever a comparison is made with a variable whose value is don't care, simulation and synthesis can differ. Therefore, the safest way to use don't care values is to do the following.

• Assign don't care values only to output ports
  
  
• Make sure that the design never reads output ports
  
  

These guidelines guarantee that when you simulate within the scope of the design, the only difference between simulation and synthesis occurs when the simulator indicates that an output is a don't care value.

If you use don't care values internally to a design, expressions Foundation Express compares to don't care values (X) are synthesized as though values are not equal to X.

For example,

if A = 'X' then

...

is synthesized as

if FALSE then

...

If you use expressions comparing values with X, pre-synthesis and post-synthesis simulation results might not agree. For this reason, Foundation Express issues the following warning.

Warning: A partial don't-care value was read in routine test line 24 in file 'test.v'  This may cause simulation to disagree with synthesis. (HDL-171)