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                    |  | To enhance Xilinx 
                        CPLD designer productivity, Xilinx offers two free, 
                        leading edge, web powered software products.  
                        
                         
                            Earlier this year, 
                            as part of the Silicon Xpresso initiative, Xilinx 
                            introduced the CPLD WebFITTER. This, industry first, 
                            interactive & on-line tool allows customers 
                            the ability to evaluate existing designs with our 
                            XC9500/XL/XV ISP CPLD families. 
                            
To augment this 
                            tool, Xilinx now offers the WebPACK, two suites 
                            of free downloadable PC based design solutions that 
                            allow customers the ability to completely design, 
                            fit and program Xilinx XC9500 Series or Xilinx CoolRunner 
                            Series CPLD devices.  
                            
                         Whether your design flow includes 
                        EDA tools like Synopsys, Synplicity or Exemplar, or 
                        you are looking for a complete design environment (including 
                        ABEL & HDL synthesis, fitting technology and programming 
                        software), WebFITTER and WebPACK allow the ultimate 
                        in flexibility. |  
 
                
                    | Xilinx 
                        CPLD WebFITTER |  
                    | 
 | Xilinx CPLD WebFITTER has broken new ground in the 
                        area of on-line silicon solution evaluation. By simply 
                        pointing to the design file and clicking the ¡®GO¡¯ 
                        button, you are moments away from the industry's best 
                        CPLD solution. Whether it's performance, cost or ease-of-use, 
                        the WebFITTER has it all. |  
                    | WebFITTER features: 
                         
                            Full fitting support for the 
                            XC9500 (5V), XC9500XL(3.3V) & XC9500XV (2.5V) 
                            devices. 
                            Accepts designs in VHDL, Verilog, 
                            ABEL, EDIF, XNF, TDF and NSR formats. 
                            Targets device via density, package, 
                            speed, voltage or automatic device selection. 
                            On-line price quotes 
                         |  
                    | 
 |  
                    | Once a design is 
                        submitted, the user is notified via email upon completion 
                        through the WebFITTER. A specific URL provides a comprehensive 
                        design evaluation summary page. Here, the user can quickly 
                        understand thier overall design statistics and device 
                        utilization. |  
                    | WebFITTER provides: 
                         
                            Links to fitting, timing and 
                            log files 
                            Targeted device datasheets 
                            On line XC9500 Series price quotes 
                            
                            Simulation and device programming 
                            files 
                            Complete on-line HELP system 
                            
                            On-line tutorials 
                         Take 
                        me to the WebFITTER Page |  
 
                
                    | Xilinx 
                        CPLD WebPACK |  
                    | 
 | The Xilinx CPLD WebPACK contains FREE downloadable 
                        software solutions for Xilinx XC9500 Series and Xilinx 
                        CoolRunner CPLD design.  Each solution provides 
                        a simple and intuitive design environment for your target 
                        Xilinx CPLD family. |  
                    | The Xilinx XC9500 Series 
                        CPLD WebPACK is a suite of three EDA design 
                        tools that can be downloaded and used individually or, 
                        when downloaded together become an integrated design 
                        environment for XC9500 Series CPLDs.  The Xilinx CoolRunner 
                        Series CPLD WebPACK includes two downloadable 
                        modules for the XPLA design entry and device programming 
                        software supporting all Xilinx CoolRunner Series CPLDs. |  
                    | 
 
                            
                                | 
 | For designers that do not currently have 
                                    EDA design entry tools, Xilinx is pleased 
                                    to offer the XC9500 HDL - ABEL Synthesis 
                                    Tools module; a complete ABEL v7.1 and 
                                    VHDL & Verilog synthesis design environment. |  After downloading and installing this module, the 
                        Project Navigator will detect if any other WebPACK modules 
                        are present. Once installed the WebPACK modules will 
                        provide complete design implementation control from 
                        within a single project window.  By using the latest version of the ABEL compiler 
                        and simulator (V7.1) and Xilinx Synthesis Technology, 
                        coupled with the industry's most widely used project 
                        navigation system, Xilinx offers the latest in an integrated 
                        PC based CPLD design environment. |  
                    | 
 |  
                    | The Project Navigator 
                        can compile ABEL, VHDL or Verilog source files. ABEL 
                        vectors can be simulated and HDL testbenches can link 
                        to third party HDL simulation tools, like Model Technology. 
                        Once compiled, the netlist can be processed through 
                        the Xilinx CPLD implementation tools, seamlessly. The 
                        necessary JEDEC file will be created and the Project 
                        Navigator will invoke the JTAG Programmer for device 
                        programming and JTAG ¡®INTEST¡¯ verification using the 
                        same ABEL vectors from your design. |  
                    | 
 
                            
                                | 
 | If you currently own a design entry tool 
                                    such as synthesis or schematic capture, 
                                    the XC9500 Device Fitter Tools module 
                                    provides all the device fitting and verification 
                                    tools needed to fit your design into any 
                                    of the Xilinx XC9500 Series CPLDs.  |  The XC9500 Device Fitter Tools module is identical 
                        to the Alliance Series v2.1i software currently available 
                        from Xilinx, just specific to the XC9500 CPLD families. 
                        This FREE downloadable module will accept either EDIF 
                        or XNF netlists and provide you with the JEDEC programming 
                        file and timing simulation netlist. |  
                    | 
                            
                                | Features Included: 
                                     
                                        Project management 
                                        with version and revision control 
                                        
                                        LogiBLOX module synthesis 
                                        
                                        Push-button implementation 
                                        flows 
                                        Timing driven fitting 
                                        technology 
                                        Fitting and timing 
                                        reports with internet enabled on-line 
                                        help 
                                        Xilinx Constraints 
                                        Editor 
                                        CPLD ChipViewer 
                                        
                                        Interactive Timing 
                                        Analyzer. 
                                     | 
 |  
                                | 
 |  
                                | The CPLD ChipViewer (a JavaTM utility) 
                                    allows for graphical pin constraint and 
                                    assignment. The tool is also used to view 
                                    a design implementation, graphically, from 
                                    the chip boundry down to individual macrocell 
                                    equations. |  |  
                    | 
 
                            
                                | 
 | The Device Programming Tools module 
                                    contains all the software necessary to perform 
                                    IEEE 1149.1 JTAG operations on both the 
                                    Xilinx XC9500 series CPLDs and Xilinx FPGA 
                                    devices that support JTAG configuration. 
                                    For CoolRunner device programming, use the 
                                    CoolRunner 
                                    PC-ISP Programming WebPACK module. |  
                            
                                | This software can be run as a stand-alone 
                                    programming tool or can be invoked from 
                                    within either the WebPACK Project Navigator 
                                    (XC9500 HDL-ABEL Synthesis Tools module) 
                                    or from within the Xilinx Design Manager 
                                    (XC9500 Device Fitter Tools module). Even 
                                    if you are not a CPLD designer, the Device 
                                    Programming Tools module allows you to get 
                                    the latest updates for FPGA device programming 
                                    as well! | 
 |  |  
                    | 
 
                            
                                | 
 | XPLA Professional v3.3 contains the latest 
                                    design development software for Xilinx CoolRunner 
                                    CPLDs. |  
                            
                                | Features Included: 
                                     
                                        Design entry (PHDL, 
                                        3rd party EDIF, ECS schematic capture 
                                        and Verilog synthesis). 
                                        Design verification 
                                        (static timing, full functional and 
                                        timing simulation, and behavioral models). 
                                        
                                        Dynamic power consumption 
                                        simulation 
                                        Device implementation 
                                        tools for the following CoolRunner CPLD 
                                        families: 
                                        
                                            22V10, XPLA, 
                                            XPLA Enhanced, XPLA2 
                                        Graphical Pin Eidtor 
                                        
                                     |  
                                | 
 |  |  
                    | 
 
                            
                                | 
 | XPLA PC-ISP v4.0 contains the latest 
                                    ISP device programming software for Xilinx 
                                    CoolRunner CPLDs. |  
                            
                                | Features Included: 
                                     
                                        Graphical dislpay 
                                        of JTAG chain, supporting up to 60 devices. 
                                        
                                        Support for non-CoolRunner 
                                        CPLDs. 
                                        Automatic cable detection 
                                        supporting the following: 
                                        
                                            CoolRunner download 
                                            cable 
                                            Xilinx JTAG download 
                                            cable 
                                            Altera Byte-Blaster 
                                            cable 
                                        ATE automatic vector 
                                        generation including SVF. 
                                     | 
 |  |  Take me to the WebPACK page |