Offsets are used to define the timing relationship between an external clock and its associated data-in or data-out pin. Using this option allows you to do the following.
Following are some of the advantages of using the OFFSET constraint.
There are basically three types of offset specifications.
Since the global and group OFFSET constraints are not associated with a single data net or component, these two types can also be entered on a TIMESPEC symbol in the design netlist with Tsid.
Schematic syntax in a TIMESPEC symbol
TSid=[TIMEGRP name] OFFSET = {IN|OUT} offset_time [units] {BEFORE|AFTER} clk_name [TIMEGRP group_name]
UCF syntax
[TIMEGRP name] OFFSET = {IN|OUT} offset_time [units] {BEFORE|AFTER} clk_name [TIMEGRP group_name];
In the UCF file, you cannot specify the TSid format.
See the next section and the “Group OFFSET” section for syntax details. As with the PERIOD and MAXDELAY timing specifications, if the same TSid is defined in the design netlist (or NCF) and the UCF file, the UCF file takes precedence.
The following subsections describe the use of each type of OFFSET in PCF and UCF files and explain the scope of each specification.
Release 1.5 supports the use of the global OFFSET constraint. Release 1.5 also supports the use of time groups within global OFFSET constraints. On a schematic, enter the global OFFSET in the TIMESPEC symbol.
UCF syntax
OFFSET = {IN|OUT} offset_time [units] {BEFORE|AFTER} clk_name [TIMEGRP group_name];
PCF syntax
OFFSET = {IN|OUT} offset_time [units] {BEFORE|AFTER} COMP clk_iob_name [TIMEGRP group_name];
offset_time is the external offset and units is an optional field that indicates the units for the offset time. The default units are nanoseconds, but the timing number can be followed by ps, ns, us, ms, GHz, MHz, or KHz to show the intended units.
The UCF syntax variable clk_name is the fully hierarchical net name of the clock net between its pad and its input buffer.
The clk_iob_name is the block name of the clock IOB.
The optional TIMEGRP group_name defines a group of registers that will be analyzed. By default, all registers clocked by clk_name will be analyzed.
IN | OUT specifies that the offset is computed with respect to an input IOB or an output IOB. For a bidirectional IOB, the IN | OUT syntax lets you specify the flow of data (input or output) on the IOB.
BEFORE | AFTER indicates whether data is to arrive (input) or leave (output) the device before or after the clock input.
All inputs/outputs are offset relative to clk_name or iob_name. For example, OFFSET IN 20 ns BEFORE clk1 dictates that all inputs will have data present at the pad at least 20 ns before the triggering edge of clk1 arrives at the pad.
The OFFSET constraint can also be used to specify a constraint for a specific data net in a UCF file or schematic or a specific input or output component in a PCF file.
Schematic syntax when attached to a net
OFFSET = {IN|OUT} offset_time [units] {BEFORE|AFTER} clk_name [TIMEGRP group_name]
UCF syntax
NET name OFFSET = {IN|OUT} offset_time [units] {BEFORE|AFTER} clk_name [TIMEGRP group_name];
PCF syntax
COMP “iob_name” OFFSET = {IN|OUT} offset_time [units] {BEFORE|AFTER} COMP “clk_iob_name” [TIMEGRP “group_name”];
The PCF file uses blocks (comps) instead of nets.
If COMP “iob_name“ is omitted in the PCF or NET “name” is omitted in the UCF, the specification is assumed to be global.
offset_time is the external offset.
units is an optional field that indicates the units for offset time. The default units are in nanoseconds, but the timing number can be followed by ps, ns, us, GHz, MHz, or KHz to indicate the intended units.
clk_iob_name is the block name of the clock IOB.
It is possible for one offset constraint to generate multiple data and clock paths (for example, when both data and clock inputs have more than a single sequential element in common).
The offset constraint examples in this section apply to the following figures.
Figure 4.11 OFFSET Example Schematic |  |
Figure 4.12 OFFSET IN Timing Diagram | |
Figure 4.13 OFFSET OUT Timing Diagram | |
OFFSET IN BEFORE defines the available time for data to propagate from the pad and setup at the synchronous element (COMP). The time can be thought of as the time differential of data arriving at the edge of the device before the next clock edge arrives at the device. See the “OFFSET Example Schematic” figure and the “OFFSET IN Timing Diagram” figure. The equation that defines this relationship is as follows.
TDATA + TSU - TCLK < TIN_BEFORE
For example, if TIN_BEFORE equals 20 ns, the following syntax applies.
Schematic syntax attached to DATA_IN
OFFSET=IN 20.0 BEFORE CLK_SYS
UCF syntax
NET DATA_IN OFFSET=IN 20.0 BEFORE CLK_SYS;
PCF syntax
COMP DATA_IN OFFSET=IN 20.0 ns BEFORE COMP CLK_SYS;
This constraint indicates that the data will be present on the DATA_IN pad at least 20 ns before the triggering edge of the clock net arrives at the clock pad.
To ensure that the timing requirements are met, the timing analysis software verifies that the maximum delay along the path DATAIN to COMP (minus the 20.0 ns offset) would be less than or equal to the minimum delay along the reference path CLOCK to COMP.
Example 2 - OFFSET IN AFTERThis constraint describes the time used by the data external to the FPGA. OFFSET subtracts this time from the PERIOD declared for the clock to determine the available time for the data to propagate from the pad and setup at the synchronous element. The time can be thought of as the differential of data arriving at the edge of the device after the current clock edge arrives at the edge of the device. See the “OFFSET Example Schematic” figure and the “OFFSET OUT Timing Diagram” figure. The equation that defines this relationship is as follows.
TDATA + TSU - TCLK < TP - TIN_AFTER
TP is the clock period.
For example, if TIN_AFTER equals 30 ns, the following syntax applies.
Schematic syntax attached to DATA_IN
OFFSET=IN 30.0 AFTER CLK_SYS;
UCF syntax
NET DATA_IN OFFSET=IN 30.0 AFTER CLK_SYS;
PCF syntax
COMP DATA_IN OFFSET=IN 30.0 ns AFTER COMP CLK_SYS;
This constraint indicates that the data will arrive at the pad of the device (COMP) no more than 30 ns after the triggering edge of the clock arrives at the clock pad. The path DATA_IN to COMP would contain the setup time for the COMP data input relative to the CLK_SYS input.
Verification is almost identical to Example 1, except that the offset margin (30.0 ns) is added to the data path delay. This is caused by the data arriving after the reference input. The timing analysis software verifies that the data can be clocked in prior to the next triggering edge of the clock.
A PERIOD or FREQUENCY is required only for offset OUT constraints with the BEFORE keyword or offset IN with the AFTER keyword.
Example 3 - OFFSET OUT AFTERThis constraint defines the time available for the data to propagate from the synchronous element to the pad. This time can also be considered as the differential of data leaving the edge of the device after the current clock edge arrives at the edge of the device. See the “OFFSET Example Schematic” figure and the “OFFSET OUT Timing Diagram” figure.
The equation that defines this relationship is as follows.
TQ + TCO - TCLK < TOUT_AFTER
For example, if TOUT_AFTER equals 35 ns, the following syntax applies.
Schematic syntax attached to Q_OUT
OFFSET=OUT 35.0 AFTER CLK_SYS
UCF syntax
NET Q_OUT OFFSET=OUT 35.0 AFTER CLOCK;
PCF syntax
COMP Q_OUT OFFSET=OUT 35.0 ns AFTER COMP CLK_SYS;
This constraint calls for the data to leave the FPGA 35 ns after the present clock input arrives at the clock pad. The path COMP to Q_OUT would include the CLOCK-to-Q delay (component delay).
Verification involves ensuring that the maximum delay along the reference path (CLK_SYS to COMP) and the maximum delay along the data path (COMP to Q_OUT) does not exceed the specified offset.
Example 4 - OFFSET OUT BEFOREThis constraint defines the time used by the data external to the FPGA. OFFSET subtracts this time from the clock PERIOD to determine the available time for the data to propagate from the synchronous element to the pad. The time can also be considered as the differential of data leaving the edge of the device before the next clock edge arrives at the edge of the device See the “OFFSET Example Schematic” figure and the “OFFSET OUT Timing Diagram” figure. The equation that defines this relationship is as follows.
TQ + TCO + TCLK < TP - TOUT_BEFORE
For example, if TOUT_BEFORE equals 15 ns, the following syntax applies.
Schematic syntax attached to Q_OUT
OFFSET=OUT 15.0 BEFORE CLK_SYS
UCF syntax
NET Q_OUT OFFSET=OUT 15.0 BEFORE CLK_SYS;
PCF syntax
COMP Q_OUT OFFSET=OUT 15.0 ns BEFORE COMP CLK_SYS;
This constraint states that the data clocked to Q_OUT must leave the FPGA 15 ns before the next triggering edge of the clock arrives at the clock pad. The path COMP to Q_OUT includes the CLK_SYS-to-Q delay (component delay). The data clocked to Q_OUT will leave the FPGA 15.0 ns before the next clock input.
Verification involves ensuring that the maximum delay along the reference path (CLK_SYS to COMP) and the maximum delay along the data path (COMP to Q_OUT) do not exceed the clock period minus the specified offset.
As in Example 2, a PERIOD or FREQUENCY constraint is required only for offset OUT constraints with the BEFORE keyword or offset IN with the AFTER keyword.
A clock register time group allows you to define a specific set of registers to which an OFFSET constraint applies based on a clock edge. Consider the following example.
Figure 4.14 Using Timegroups with Registers | |
You can define time groups for the registers A, B and C, even though these registers have the same data and clock source. The syntax is as follows.
Schematic syntax in TIMEGRP primitive
AB=RISING FFS
C =FALLING FFS;
UCF /PCF syntax
TIMEGRP AB=RISING FFS;
TIMEGRP C =FALLING FFS;
Schematic syntax attached to DATA
OFFSET=IN 10 BEFORE CLOCK TIMEGRP AB
OFFSET=IN 20 BEFORE CLOCK TIMEGRP C
UCF syntax
NET DATA OFFSET=IN 10 BEFORE CLOCK TIMEGRP AB;
NET DATA OFFSET=IN 20 BEFORE CLOCK TIMEGRP C;
PCF syntax
COMP DATA OFFSET=IN 10 BEFORE COMP CLOCK TIMEGRP AB;
COMP DATA OFFSET=IN 20 BEFORE COMP CLOCK TIMEGRP C;
Even though the registers A, B and C have a common data and clock source, timing analysis applies two different offsets (10 ns and 20 ns). Registers A and B belong to the offset with 10 ns and Register C belongs to the offset with 20 ns.
However, you must use some caution when using timegroups with registers. Consider the following diagram.
Figure 4.15 Problematic Timegroup Definition | |
This circuit is identical to the “Using Timegroups with Registers” figure except that an inverter has been inserted in the path to Register B. In this instance, even though this register is a member of the time group whose offset triggers on the rising edge, the addition of the inverter classifies register B as triggering on the falling edge like Register C.
Normally, the tools will move an inverter to the register, in which case, B would be a part of the timegroup “Falling”. However if the clock is gated with logic that inverts, then the inverter will not become part of the register. In that case, one way to solve this problem is to create a timegroup with an exception for Register B. See the “Creating Groups by Exclusion” section for details.
You can also define OFFSET constraints within the TIMESPEC primitive with a leading TIMEGRP reference.
Schematic syntax in TIMESPEC primitive
TSidentifier=TIMEGRP name OFFSET= {IN|OUT} offset_time [units] {BEFORE|AFTER} clk_name [TIMEGRP group_name]
The UCF and PCF syntax do not require the TSidentifier.
UCF syntax
[TIMEGRP name] OFFSET= {IN|OUT} offset_time [units] {BEFORE|AFTER} clk_name [TIMEGRP group_name];
PCF syntax
[TIMEGRP name] OFFSET= {IN|OUT} offset_time [units] {BEFORE|AFTER} COMP clk_iob_name [TIMEGRP group_name];
The timing group specified at the beginning has a different purpose than the timegroup specified at the end. The first time group is a list of data pads that the OFFSET applies to, while the last time group (register time group) is a list of synchronous elements that specifies which register elements clocked by clk_name or clk_iob_name should be analyzed.
If the first group has FFs or the second group has PADS, NGDBuild generates an error.
offset_time is the external offset.
units is an optional field that indicates the units for offset time. The default units are in nanoseconds, but the timing number can be followed by ps, ns, us, GHz, MHz, or KHz to indicate the intended units.
clk_iob_name is the block name of the clock IOB.
