Register Ordering

When you map a design containing registers, the MAP software can optimize the way the registers are grouped into CLBs (slices for Virtex - in Virtex there are two slices per CLB). This optimized mapping is called “register ordering.”

A CLB (or Virtex slice) has two flip-flops, so two register bits can be mapped into one CLB. For PAR (Place And Route) to place a register in the most effective way, you often want as many pairs of contiguous bits as possible to be mapped together into the same CLBs (for example, bit 0 and bit 1 together in one CLB, bit 2 and bit 3 in another).

MAP pairs register bits (performing “register ordering”) if it can recognize that a series of flip-flops comprise a register. When you create your design, you can name register bits in a way that ensures they are mapped using register ordering.

NOTE

MAP does not perform register ordering on any flip-flops which have BLKNM, LOC, or RLOC properties attached to them. The BLKNM, LOC, and RLOC properties define how blocks are to be mapped, and these properties override register ordering.

To be recognized as a candidate for register ordering, the flip-flops must have these characteristics.

• The flip-flops must share a common clock signal and common control signals (for example, Reset and Clock Enable).
  
  
• The flip-flop output signals must all be named according to this convention.
  
  
  • Output signal names must begin with a common root containing at least one alphabetic character.
    
    
  • The names must end with numeric characters or with numeric characters surrounded by parentheses ( “(“ and “)” ), angle brackets ( “<“ and “>” ), or square brackets ( “[“ and “]” ).
    
    For example, acceptable output signal names for register ordering are
    
    

    data1	addr(04)	bus<1>
    data2	addr(08)	bus<2>
    data3	addr(12)	bus<3>
    data4	addr(16)	bus<4>
    		bus<5>

    
    
    
    

If a series of flip-flops are recognized as candidate for register ordering, they are paired in CLBs in sequential numerical order. For example, in the first set of names shown above, data1 and data2, are paired in one CLB, while data3 and data4 are paired in another.

In the example below, no register ordering is performed, since the root names for the signals are not identical.

NOTE

In the OrCAD^® schematic capture program, an underbar (_) and a sheet number are appended to each output signal name (for example, data01_1 or add15_12). In order to allow register ordering on designs developed using the OrCAD tools, MAP checks each signal name to see if it ends with an underbar followed by numeric characters.

When it finds a signal with this type of name, MAP ignores the underbar and the numeric characters when it considers the signal for register ordering. For example, if signals are named data00_1 and data01_2, MAP considers them as data00 and data01 for purposes of register ordering. These two signals are mapped to the same CLB.

Two extra notes:

• MAP does not change signal names when it checks for underbars - it only ignores the underbar and the number when it checks to see if the signal is a candidate for register ordering.
  
  
• Because of the way signals are checked, make sure you don't use an underbar as your bus delimiter. If you name a bus signal data0_01 and a non-bus signal data1, MAP sees them as data0 and data1 and register orders them even though you do not want them register ordered.
  
  

When you run the MAP command the default setting performs register ordering. If you specify the -r option when you run the command, the software does not perform register ordering and maps the register bits as if they were unrelated.

Virtex does not support the -r option.