In guided mapping, an existing NCD is used to guide the current MAP run. The guide file may be from any stage of implementation: unplaced or placed, unrouted or routed.
Virtex does not support guided mapping.
The following figure shows the flow used when you perform guided mapping.
Figure 6.3 Guided Mapping |  |
In the EXACT mode the mapping in the guide file is followed exactly. Any logic in the input NGD file that matches logic mapped into the physical components of the NCD guide file is implemented exactly as in the guide file. Mapping (including signal to pin assignments), placement and routing are all identical. Logic that is not matched to any guide component is mapped by a subsequent mapping step.
If there is a match in EXACT mode, but your constraints would conflict with the mapping in the guide file component, an error is posted. If an error is posted, you can modify the constraints to eliminate conflicts, change to the LEVERAGE guide mode (which is less restrictive), modify the logical design changes to avoid conflicts, or abandon using guided design.
In the LEVERAGE mode, the guide design is used as a starting point in order to speed up the design process. However, in cases where the guided design tools cannot find matches or your constraints rule out any matches, the logic is not guided.
Whenever the guide design conflicts with the your mapping, placement or routing constraints, the guide is ignored and your constraints are followed.
Since the LEVERAGE mode only uses the guide design as a starting point for mapping, MAP may subsequently choose to alter the mapping to improve the speed or density of the implementation (for example, MAP may choose to collapse additional gates into a guided CLB).
For Verilog® or VHDL netlist input designs, re-synthesizing modules typically cause signal and instance names in the resulting netlist to be significantly different from the netlist obtained in earlier synthesis runs. This occurs even if the source level Verilog or VHDL code only contains a small change. Because guided mapping depends on signal and component names, synthesis designs often have a low "match rate" when guided. Therefore, guided mapping is not recommended for most synthesis-based designs, although there may be cases where it could be a successful alternative technique.
