Design Manager Fundamentals

You can perform multiple functions from within the Design Manager, such as launching Xilinx tools and programming a device. In addition, the Design Manager allows you to manage your projects, design versions, and implementation revisions.

Design Manager Capabilities

You can use the Design Manager to perform the following functions.

• Organize and manage your design implementation data
  
  
• Target different devices
  
  
• Manage data for and access to the following tools in the Xilinx Design Manager system. The tools differ for FPGA and CPLD families.
  
  
  • Flow Engine (FPGA and CPLD)
    
    
  • Timing Analyzer (FPGA and CPLD)
    
    
  • Floorplanner (Spartan and XC4000 families only)
    
    
  • PROM File Formatter (FPGA)
    
    
  • Hardware Debugger (FPGA)
    
    
  • EPIC Design Editor (FPGA)
    
    
  • JTAG Programmer (CPLD)
    
    
• Generate timing simulation data for external simulation tools
  
  
• Generate configuration data
  
  
• Program a device
  
  

Design Management Functions

The Design Manager handles the following design management functions.

Managing Projects

The Design Manager window displays all Xilinx data related to a single project. A project includes all design versions and implementation revisions that are created as you implement your design. You can work with multiple projects, but only one is active at a time. The hierarchical structure shows you the relationships of the data elements to each other.

Managing Design Versions

You create your design using third party front-end tools such as schematic, Verilog, and VHDL entry. The Design Manager reads in the design netlist and creates a design version in the Design Manager project view. The Design Manager manages the design versions that it creates.

Each time you change the logic of your design, you must create a new design version. The Design Manager reads in the modified design to create the new design version. Old design versions are overwritten if specified.

You can try modified versions of your design and easily keep track of them. Each new file that you create becomes a new design version and is assigned a design version name by the Design Manager. You can choose any one of the available design versions for processing. For each design version, you can create multiple implementation revisions. For each implementation revision, you can target a different device family and choose different processing strategies, such as optimizing for area or speed.

NOTE

The Design Manager saves design versions in the Xilinx database format, not in the format of the front-end editor.

Managing Implementation Revisions

After you create a design version, you can try different implementation strategies on that design. This method allows you to vary how your design is implemented in order to achieve your design objectives. For example, you can maximize speed and density in your design by controlling the implementation settings.

The data associated with each of these implementation strategies is called an implementation revision. Each implementation revision contains the data files and reports that are created based on a specific set of implementation strategies. You can delete implementation revisions that are no longer useful.

Design Management Basic Procedure

The typical procedure for managing a design is as follows.

1. In your design entry tool, create a design.
   
   
2. In your design entry tool, output your design as an EDF, EDIF, EDN, SEDIF, PLD, SXNF, XNF, or XTF file. The PLD format is supported for CPLDs only.
   
   
3. In the Design Manager, open an existing project or create a new project in which to implement your logic design.
   
   
4. Implement your design.
   
   
   • If necessary, choose a different target device in which to implement your design. The initial target device is specified in the input design or when you create a new implementation revision.
     
     
   • Select option templates to specify implementation, simulation, and configuration options. You can use the default templates, an existing template, or a new template.
     
     
   • Run your design implementation and create timing simulation files and a device programming file.
     
     
5. Review your design reports to verify that your design fits within the target device and that your timing requirements are met.
   
   
6. If your design requirements are not met, you can do any of the following and process your design again.
   
   
   • Change your logic design.
     
     
   • Choose a different target device, package, or speed grade.
     
     
   • Define a different set of implementation, simulation, or configuration options.