Generating Pin Locking Constraints

You can generate pin locking constraints in your UCF file for use with other Xilinx implementation tools. Pinout information is taken from a placed NCD file for FPGAs or a fitted GYD file for CPLDs.

To Generate Pin Locking Constraints

1. In the Design Manager project view, select an implementation revision icon.
   
   
2. Select Design Lock Pins from the Design Manager.
   
   
3. When a confirmation dialog box appears, click Yes.
   
   Pin locking constraints that you created with this command are added to your UCF file in the PINLOCK section.
   
   
4. After the constraints are added, the Lock Pins Status dialog box appears, as shown in the “Lock Pins Status Dialog Box” figure of the “Menu Commands” chapter. Click View Lock Pins Report to view the report.
   
   If you want to view the report after you have dismissed the Lock Pins Status dialog box, use the Utilities Lock Pins Report from the Design Manager.