XC9500 Implementation Template Dialog Box

Click the Basic, Advanced, Timing Reports, Interface, or Programming tab to access the different options within the Implementation Template dialog box. Use the different tabs of this dialog box to set the options described in this section.

Click OK to accept the template, click Cancel to exit the dialog box without changing any settings, click Default to set the default options which are optimized for speed, or click Help to obtain online help.

NOTE

In addition to the default template, there is another preset implementation template: Optimize for Density. The defaults described in the following sections only apply to the default (Optimize for Speed) template.

XC9500 Basic Tab

Use the Basic tab, shown in the following figure, to set these options.

Figure 5.56 XC9500 Implementation Template Basic Tab

Use Global Clock(s)

Select this option to convert the p-term clock to a global clock. The global clock may allow you to meet your timing constraints more easily. By default, this option is on.

Use Global Output Enable(s)

Select this option to convert the p-term output enable to global output enable. Global output enable may allow you to meet your timing constraints more easily. By default, this option is on.

Use Global Set/Reset

Select this option to convert the p-term set/reset to global set/reset. Global set/reset may allow you to meet your timing constraints more easily. By default, this option is on.

Use Timing Constraints

Select this option to indicate that you want the software to use your timing constraints to perform timing-driven optimization in the fitting of your design. For this option to be useful, you must have previously created a timing constraints file or you must have included timing constraints in your design. By default, this option is on.

Use Design Location Constraints

Select this option to indicate that you want to use pinout and macrocell location information in the design file or in a constraint file. Deselect this option to allow the fitter to place pins and logic anywhere or as specified in the guide file. By default, this option is on.

Create Programmable Ground Pins on Unused I/O

Select this option to indicate that you want all unused I/O pads to be configured as ground pins. This may reduce ground bounce. By default, this option is off.

Macrocell Power Setting

Use this option to control device power consumption. Select Std (standard), Low, or Timing Driven to set the default power mode for the macrocells used to implement the design. The default is Std.

NOTE

Any explicit power control statements in the design or constraints file have precedence over the Default Power Setting.

• Std
  
  Select Std to set the power mode for the macrocells to higher speed and higher power.
  
  
• Low
  
  Select Low to reduce power consumption and reduce speed.
  
  
• Timing Driven
  
  Select Timing Driven to set the power consumption based on your timing constraints.
  
  

Output Slew Rate

Use this option to modify the output slew rate. Limiting the slew rate reduces output switching surges in the device. You can control the transition time of device output pins by setting the slew rate to Fast, Slow, or Timing Driven. The default is Fast.

NOTE

Any explicit slew rate control statements in the design or constraints file have precedence over the Output Slew Rate. This setting has no effect on third-party tools that create explicit slew rate statements.

• Fast
  
  Select Fast to use more current and enable faster logic responses.
  
  
• Slow
  
  Select Slow to use less current and avoid ground bounce.
  
  
• Timing Driven
  
  Select Timing Driven to control the transition time based on your timing constraints.
  
  

XC9500 Advanced Tab

Use the Advanced tab, shown in the following figure, to set these options.

Figure 5.57 XC9500 Implementation Template Advanced Tab

Use Timing Optimization

Select this option to perform timing optimization. Timing optimization shortens the critical paths and allocates the fastest resources for a design, assuming that all paths are equally critical. In some cases, timing optimization will trade density for speed. By default, this option is on.

Use Multi-level Logic Optimization

This option simplifies the total number of logic expressions in a design, and then collapses the logic in order to meet user objectives such as density, speed and timing constraints. This optimization targets CPLD architecture, making it possible to collapse to the macrocell limits, reduce levels of logic, and minimize the total number of p-terms.

Multi-level Logic Optimization optimizes combinatorial logic from your design. Combinatorial logic includes the following types of logic.

• Register-to-register logic
  
  
• Pad-to-register logic
  
  
• Register-to-pad logic
  
  
• Pad-to-pad logic
  
  

Multi-level Logic Optimization operates on combinatorial logic according to the following rules.

• If timing constraints are set, the program optimizes for speed to meet timing constraints.
  
  
• If timing constraints are not set, the program optimizes either for speed or density, depending on the user setting for the Use Timing Optimization option.
  
  
  • If Use Timing Optimization is turned on, the combinatorial logic will be mapped for speed.
    
    
  • If Use Timing Optimization is turned off, the combinatorial logic will be mapped for density. The goal of optimization will then be to reduce the total number of p-terms.
    
    
• Logic marked with the attribute MINIMIZE=OFF will not be extracted or optimized.
  
  

By default, this option is on.

Use Advanced Fitting

Select this option to enable an advanced fitting strategy that favors placing signals with common inputs in the same function block. This usually allows you to pack more logic into the same device. Disable this option if the software has trouble fitting a design that used to fit with an older version of software. By default, this option is on.

Enable D <--> T Type Transform Optimization

Select this option to allow the software to convert D-type flip-flops to T-type flip-flops. This option allows the software to choose the implementation that requires the smaller amount of logic resources. By default, this option is on.

Collapsing PTerm Limit

This option controls the degree to which a design netlist is flattened. A logic gate can collapse forward into a subsequent gate only if the number of product terms in the resulting logic function does not exceed the p-term limit. If the path delay of a logic function is not acceptable, increase the p-term limit to allow the larger functions to be further flattened. Choose a number from 2 to 90. The default p-term limit for the XC9500 device family is 20 p-terms.

XC9500 Only - Use Local Macrocell Feedback

Select this option to enable the software to use local macrocell feedback whenever possible. The local feedback path (from a macrocell-output to an input of the same function block) takes less time than the global feedback path. Using local feedback can speed up your design but can also make it difficult to keep the same timing after a design change.

To take maximum advantage of local feedback, control the placement to group appropriate signals into the same function block. In order to fit a design, the software may require wire-ANDing in the interconnect which can prevent local feedback use. However, you can force a local feedback by applying a timing constraint and assigning the signals to the same function block. This method prevents wire-ANDing of local feedback signal and works even if you disable the Use Local Macrocell Feedback option. By default, this option is on.

NOTE

The XC9536 device does not have local feedback.

XC9500 Only - Use Local Pin Feedback

Select this option to enable the software to use local I/O pin feedback whenever possible. The pin feedback path takes less time than the FastCONNECT^™ path. The software uses the pin feedback path instead of the FastCONNECT path for output pin signals that do not have 3-state control or Slow slew rate. By default, this option is on.

XC9500 Only/XC9500XL Only - Collapsing Input Limit

This option controls the degree to which a design netlist is flattened. A logic gate can collapse forward into a subsequent gate only if the number of inputs in the resulting logic function does not exceed the input limit. If the path delay of a logic function is not acceptable, increase the input limit to allow the larger functions to be further flattened. For XC9500 devices, choose a number from 2 to 36. For XC9500XL devices, choose a number from 2 to 54. The default for both is 36.

XC9500 Timing Reports Tab

Use the Timing Reports Tab, shown in the following figure, to set these options.

Figure 5.58 XC9500 Implementation Template Timing Reports Tab

Produce Post Fitting Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is fitted. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Timing Report Format

This option allows you to choose the level of detail given in your timing report. The default is Summary.

• Summary
  
  Select Summary to generate a report that contains summary information and design statistics.
  
  
• Detailed
  
  Select Detailed to generate a report that lists delay information for all nets and paths.
  
  

XC9500 Programming Tab

Use the Programming tab, shown in the following figure, to set these options.

Figure 5.59 XC9500 Implementation Template Programming Tab

Signature/User Code

Select Use <design name> or enter a unique text string in the Specify As field to identify the configuration data. You can enter a string of up to four alphanumeric characters. The device programmer can read the signature, and the person running the device programmer can verify that the correct configuration data file is loaded. Use the JTAG Programmer to identify the configuration data signature (usercode) of a programmed XC9500 or XC9500XL device. The default is Use <design name>.

Jedec Test Vector File

Use this option to include a TMV file in your JEDEC file. The TMV file is a test vector file generated when ABEL compiles a design containing user test vectors. Click Browse to look for a TMV file.

XC9500 Interface Tab

Use the Interface tab, shown in the following figure, to set the translation options.

Figure 5.60 XC9500 Implementation Template Interface Tab

The XC9500 Interface tab is identical to the tab described in the “Spartan Interface Tab” section.