Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Template dialog box. Use the different tabs of this dialog box to set the options described in this section.
Click OK to accept the template, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.
Use the XC9500 General tab, shown in the following figure, to set these options.
Figure 5.61 XC9500 Simulation Template General Tab |  |
Specify the netlist format to use for simulation. The following formats are available. The default is EDIF.
Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.
Use the XC9500 VHDL/Verilog tab, shown in the following figure, to set the VHDL or Verilog options.
Figure 5.62 XC9500 Simulation Template VHDL/Verilog Tab | |
The XC9500 VHDL/Verilog tab is identical to the tab described in the “Spartan VHDL/Verilog Tab” section.
Use the XC9500 EDIF tab, shown in the following figure, to set the EDIF options.
Figure 5.63 XC9500 Simulation Template EDIF Tab | |
The XC9500 EDIF tab is identical to the tab described in the “Spartan EDIF Tab” section.
