Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Template dialog box. Use the different tabs of this dialog box to set the options described in this section.
Click OK to accept the template, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.
Use the Spartan General tab, shown in the following figure, to set these options.
Figure 5.6 Spartan Simulation Template General Tab |  |
Specify the netlist format to use for simulation. The following formats are available. The default is EDIF.
Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist. By default, this option is on.
Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.
Use the Spartan VHDL/Verilog tab, shown in the following figure, to set these options.
Figure 5.7 Spartan Simulation Template VHDL/Verilog Tab | |
This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The default name of the Global Set/Reset port depends on the target device family as described in the following table.
| Device Family | Port Name | When Top-Level Global Set/Reset Port Appears | Polarity |
|---|---|---|---|
| Spartan | GSR | per design or when option is used | active-High |
| Virtex | GSR | per design or when option is used | active-High |
| XC3000 | GR | always | active-Low |
| XC4000 | GSR | per design or when option is used | active-High |
| XC5200 | GR | per design or when option is used | active-High |
| XC9500 | PRLD | when option is used | active-High |
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.
By default, this option is off.
This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.
By default, this option is off.
This option is only used if the global tristate net is not driven.
This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension. By default, this option is off.
This option writes a library path pointing to the SIMPRIM library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.
`uselib dir=$XILINX/verilog/data libext=.vmd
By default, this option is off.
This option is supported for Verilog only.
This option writes out a signal-to-pin mapping file. The file has a .pin extension. By default, this option is off.
This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy. By default, this option is off.
Use the Spartan EDIF tab, shown in the following figure, to set these options.
Figure 5.8 Spartan Simulation Template EDIF Tab | |
Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen. The default is Generic.
This option writes out a flattened netlist. By default, this option is on.
The following options are enabled only if you specify Generic as the CAE Vendor.
