Spartan Configuration Template Dialog Box

Click the Configuration, Startup, Readback, or Tie tab to access the different options within the Configuration Template dialog box. Use the different tabs of this dialog box to set the options described in this section.

Click OK to accept the template, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

Spartan Configuration Tab

Use the Configuration tab, shown in the following figure, to set these options.

Figure 5.9 Spartan Configuration Template Configuration Tab

Configuration Rate

The Spartan device uses an internal configuration clock, CCLK, when configuring in a master mode. The configuration rate option allows you to select the rate for this clock. The following options are available. The default is Slow.

Slow

Select Slow to set the configuration clock rate to 1 MHz (nominal).
Fast

Select Fast to set the configuration clock rate to 8 MHz (nominal).

Threshold Levels (5 Volt Spartan Parts Only)

The Threshold Levels field contains the following options.

NOTE

These options are supported for the Spartan family only. They are not supported for the SpartanXL family.

Inputs

Specify one of the following input options. The default is Read from Design.
- TTL
  
  Select TTL to specify TTL-compatible inputs.
- CMOS
  
  Select CMOS to specify CMOS-compatible inputs.
- Read from Design
  
  Select Read from Design to specify the TTL/CMOS input level included in the physical contraints (PCF) file.
Outputs

Specify one of the following output options. The default is Read from Design.
- TTL
  
  Select TTL to specify TTL-compatible output.
- CMOS
  
  Select CMOS to specify CMOS-compatible outputs.
- Read from Design
  
  Select Read from Design to specify the TTL/CMOS output level included in the PCF file.

Configuration Pins

The Configuration Pins field contains the following options.

NOTE

You cannot use these pins to set the configuration mode or use them as user I/Os.

TDO

The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.
- Float
  
  Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.
- PullUp
  
  Select PullUp to enable a pull-up on the TDO pin.
- PullDown
  
  Select PullDown to enable a pull-down on the TDO pin.
Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.
- Float
  
  Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.
- PullUp
  
  Select PullUp to enable an internal pull-up resistor on the DONE pin in Spartan devices. Select this option only if you do not connect an external pull-up resistor to this pin.
Power Down

NOTE
This option is supported for SpartanXL devices only.

The Power Down pin allows the FPGA to exist in a standby mode which consumes less power. The FPGA enters this standby mode when the Power Down pin is driven Low. The default is PullUp.
- Float
  
  Select Float to disable the pull-up resistor on the Power Down pin. Use this option if you will use the Power Down pin but will not tristate it.
- PullUp
  
  Select PullUp to enable an internal pull-up resistor on the Power Down pin. You must use this option if the Power Down pin is not connected in your design, or if the signal driving this pin could be in a tristate condition.

Perform CRC During Configuration

This option enables Cyclic Redundancy Checking (CRC) error checking during configuration. If enabled, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each data frame in the configuration bitstream. This allows the device to perform a CRC check on the bitstream during the configuration process. If disabled, the device performs a simple check for the 0110 pattern at the end of each frame in the configuration data. By default, this option is on.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.

Spartan Startup Tab

Use the Startup tab, shown in the following figure, to set these options.

Figure 5.10 Spartan Configuration Template Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK or a User Clock. The default is CCLK.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.
User Clock

Select User Clock to synchronize to a user-defined signal connected to the CLK pin of the STARTUP symbol.

Synchronize Start-up to DONE Input Pin

The startup sequence of the device can be synchronized with the signal on the DONE pin. Deselect this option to begin the startup sequence when the configuration memory is full. Select this option to begin the startup sequence when the signal on the DONE pin goes High. By default, this option is off.

Output Events

There are three major output events which occur during a device startup.

Done (DONE pin going High)
Enable Outputs (device outputs no longer tristated)
Release Set/Reset (Global Set/Reset signal deasserted)

Depending on the settings for Startup Clock and Synchronize Start-up to Done Input pin, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

Table 5_2 Output Events Options Matrix

	CCLK		User Clock
	Sync	No Sync	Sync	No Sync
DONE	C1-C3	C1-C4	C1, U2	C1, U2-U4
Enable Outputs	C2, C3, DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
Release Set/Reset	C2, C3, DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4

The definitions of the possible output events settings are as follows.

C1 - first-Cclk rising edge after the length count is met

C2 - second-Cclk rising edge after the length count is met

C3 - third-Cclk rising edge after the length count is met

C4 - fourth-Cclk rising edge after the length count is met

U2 - second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3 - third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4 - fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

DI - when the DoneIn signal goes High

DI+1 - first-Cclk or valid-user-clock rising edge, depending on the selection of startup-Clk, after DoneIn goes High

DI+2 - second-Cclk or valid-user-clock rising edge, depending on the selection of startup-Clk, after DoneIn goes High

Spartan Readback Tab

Use the Readback tab, shown in the following figure, to set these options.

Figure 5.11 Spartan Configuration Template Readback Tab

Readback Clock

The readback data can be clocked out by either CCLK or a User Clock. The default is CCLK.

CCLK

Select CCLK to clock out the readback data through an internal clock provided in the FPGA device.
User Clock

Select User Clock to clock out the readback data through a user-defined signal connected to the CLK pin of the READBACK symbol.

Enable Bitstream Verification and In-Circuit Hardware Debugging

Use this option to activate or deactivate the readback capability of the configuration bitstream. To activate this feature, select this option and include the READBACK symbol in your design. Enabling this option generates a .ll file. By default, this option is on.

Abort Readback When TRIG Goes Inactive

Use this option to abort the readback sequence. Select this option to terminate the readback sequence when the device detects a High-to-Low transition on the TRIG pin of the READBACK symbol. By default, this option is off.

Spartan Tie Tab

Use the Tie tab, shown in the following figure, to set these options.

Figure 5.12 Spartan Configuration Template Tie Tab

Tie Unused Interconnect

Select this option to cause all unused interconnect to be tied to a logic Low or to a known level, keeping internal noise and power consumption to a minimum. When you use this option, Design Rule Check (DRC) runs first. After DRC, this option does the following.

Ties all possible unused interconnect to unused CLB outputs and configures those outputs with a logic Low (F=0 or G=0)
Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical
Attempts to tie remaining interconnect to the global primary or secondary clock buffer outputs

By default, this option is off.

Tie Options - Use Critical Nets as Last Resort

Select this option to use the nets marked as critical to complete the tiedown process if necessary. Use this option as a last resort after an attempt is made to use nets not marked critical. By default, this option is off.