Virtex Implementation Template Dialog Box

Click the Optimize and Map, Place and Route, Timing Reports, or Interface tab to access the different options within the Implementation Template dialog box. Use the different tabs of this dialog box to set the options described in this section.

Click OK to accept the template, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

Virtex Optimize and Map Tab

Use the Optimize and Map tab, shown in the following figure, to set these options.

Figure 5.13 Virtex Implementation Template Optimize and Map Tab

Logic Optimization Options

The Logic Optimization Options field contains the following options.

• Trim Unconnected Logic
  
  Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.
  
  
• Replicate Logic to Allow Logic Level Reduction
  
  Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.
  
  

Map Options

The Map Options field contains the Pack I/O Registers/Latches into IOBs for option. This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

• Inputs Only
  
  Select Inputs Only to pack flip-flops or latches into input I/O cells.
  
  
• Outputs Only
  
  Select Outputs Only to pack flip-flops or latches into output I/O cells.
  
  
• Inputs and Outputs
  
  Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.
  
  
• Off
  
  Select Off to pack flip-flops or latches as specified by your design entry method.
  
  

Virtex Place and Route Tab

Use the Place and Route tab, shown in the following figure, to set these options.

Figure 5.14 Virtex Implementation Template Place and Route Tab

Place & Route Effort Level

Use this option to specify the algorithms that the placer and router use to place and route a design. Use the Place & Route Effort Level slider bar to select an effort level setting of 1, 2, 3, 4, or 5. Higher effort provides better place and route results at the expense of longer run times. The default value is 2.

Router Options

Use the Run _ Routing Passes option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At place and route effort levels of 3, 4, or 5, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels of 1 or 2, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. The default is Auto.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses the timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.

Virtex Timing Reports Tab

Use the Timing Reports tab, shown in the following figure, to set the timing report options.

Figure 5.15 Virtex Implementation Template Timing Reports Tab

The Virtex Timing Reports tab is identical to the tab described in the “Spartan Timing Reports Tab” section.

Virtex Interface Tab

Use the Interface tab, shown in the following figure, to set the translation options.

Figure 5.16 Virtex Implementation Template Interface Tab

The Virtex Interface tab is identical to the tab described in the “Spartan Interface Tab” section.

NOTE

In Virtex devices, the following components are not reset by the GSR signal: LUT RAM, Block RAM content, DLL, and SRL.